sdram can miss command transitions

[osresearch]

It looks like the sdram_controller can miss read/write commands if they occur when a refresh is happening. It checks for edges on the enable pins only if state == IDLE:

  if (state == IDLE)
     if (rd_enable && !rd_enable_prev)
          begin
          next = READ_ACT;
          command_nxt = CMD_BACT;

but the rd_enable_prev and wr_enable_prev are updated on every clock cycle:

always @ (posedge clk)
   begin

    wr_enable_prev <= wr_enable;
    rd_enable_prev <= rd_enable;

[osresearch]

I changed sdram-controller to use a level-triggered rd/wr enable and have it signal when it has started the operation. This allows small read/write tests to work fairly reliably and avoids the missing commands:

osresearch@402d3d0

However, on a larger random read/write test it fails quite often. On a linear write and read back about 1.3% errors. On a random read/write there are around 99% errors, although the test followsup with re-reading the same address the error rate is around 0.7%.

[ombhilare999]

Now we are using litedram + serv for sdram, it passed the litex mem test.
https://twitter.com/QwertyEmbedded/status/1418128122042486787

regards,
omkar bhilare
ombhilare999@gmail.com