Advertise MLEM tapeout

povik · Dec 16, 2024 · 09faefb · 09faefb
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 ## Status
 
+<img align="right" width="150" height="150" src="docs/mlem.jpg">
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+*News:* ETH Zürich has used yosys-slang for a chip tapeout. [Meet MLEM](http://asic.ethz.ch/2024/MLEM.html).
+
 *News:* The [Microelectronics Design Center](https://dz.ethz.ch/) at ETH Zürich is now sponsoring yosys-slang development for usage in ASIC synthesis flows!
 
 yosys-slang understands a synthesizable subset of SystemVerilog. Please open GitHub issues for missing features and/or confusing error messages.

diff --git a/docs/mlem.jpg b/docs/mlem.jpg