Implement ==? !=?

povik · Sep 28, 2024 · f27f116 · f27f116
1 parent 767384d
commit f27f116
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Showing 5 changed files with 47 additions and 2 deletions.
diff --git a/src/builder.cc b/src/builder.cc
@@ -351,6 +351,7 @@ SigSpec RTLILBuilder::Unop(IdString op, SigSpec a, bool a_signed, int y_width)
 		OP(reduce_and)
 		OP(reduce_xor)
 		OP(reduce_xnor)
+		OP(reduce_bool)
 #undef OP
 	}
 

diff --git a/src/diag.cc b/src/diag.cc
@@ -34,6 +34,8 @@ namespace diag {
 	slang::DiagCode UnrollLimitExhausted(slang::DiagSubsystem::Netlist, 1022);
 	slang::DiagCode NoteLoopContributes(slang::DiagSubsystem::Netlist, 1023);
 
+	slang::DiagCode NonconstWildcardEq(slang::DiagSubsystem::Netlist, 1023);
+
 	slang::DiagGroup unsynthesizable("unsynthesizable", {IffUnsupported, SignalSensitivityAmbiguous, GenericTimingUnsyn, BothEdgesUnsupported, ExpectingIfElseAload,
 														 IfElseAloadPolarity, IfElseAloadMismatch});
 	slang::DiagGroup sanity("sanity", {EdgeImplicitMixing});
@@ -88,6 +90,9 @@ namespace diag {
 
 		engine.setMessage(NoteLoopContributes, "loop contributes to unroll tally");
 		engine.setSeverity(NoteLoopContributes, slang::DiagnosticSeverity::Note);
+
+		engine.setMessage(NonconstWildcardEq, "wildcard equality unsynthesizable with non-constant right operand");
+		engine.setSeverity(NonconstWildcardEq, slang::DiagnosticSeverity::Error);
 	}
 };
 };
diff --git a/src/diag.h b/src/diag.h
@@ -31,6 +31,7 @@ extern slang::DiagCode MemoryNotInferred;
 extern slang::DiagCode NoteUsageBlame;
 extern slang::DiagCode UnrollLimitExhausted;
 extern slang::DiagCode NoteLoopContributes;
+extern slang::DiagCode NonconstWildcardEq;
 void setup_messages(slang::DiagnosticEngine &engine);
 };
 };
diff --git a/src/slang_frontend.cc b/src/slang_frontend.cc
@@ -1831,6 +1831,29 @@ RTLIL::SigSpec SignalEvalContext::operator()(ast::Expression const &expr)
 			RTLIL::SigSpec left = (*this)(biop.left());
 			RTLIL::SigSpec right = (*this)(biop.right());
 
+			bool invert;
+			switch (biop.op) {
+			case ast::BinaryOperator::WildcardEquality:
+				invert = false;
+				if (0) {
+			case ast::BinaryOperator::WildcardInequality:
+				invert = true;
+				}
+				if (!right.is_fully_const()) {
+					// TODO: scope
+					netlist.realm.addDiag(diag::NonconstWildcardEq, expr.sourceRange);
+					ret = netlist.canvas->addWire(NEW_ID, expr.type->getBitstreamWidth());
+					return ret;
+				}
+				return netlist.Unop(
+					invert ? ID($logic_not) : ID($reduce_bool),
+					netlist.EqWildcard(left, right),
+					false, expr.type->getBitstreamWidth()
+				);
+			default:
+				break;
+			}
+
 			bool a_signed = biop.left().type->isSigned();
 			bool b_signed = biop.right().type->isSigned();
 
@@ -1853,8 +1876,6 @@ RTLIL::SigSpec SignalEvalContext::operator()(ast::Expression const &expr)
 			case ast::BinaryOperator::GreaterThan:		type = ID($gt); break;
 			case ast::BinaryOperator::LessThanEqual:	type = ID($le); break;
 			case ast::BinaryOperator::LessThan:			type = ID($lt); break;
-			//case ast::BinaryOperator::WildcardEquality;
-			//case ast::BinaryOperator::WildcardInequality;
 			case ast::BinaryOperator::LogicalAnd:	type = ID($logic_and); break;
 			case ast::BinaryOperator::LogicalOr:	type = ID($logic_or); break;
 			case ast::BinaryOperator::LogicalImplication: type = ID($logic_or); left = netlist.LogicNot(left); a_signed = false; break;

diff --git a/tests/various/expr.sv b/tests/various/expr.sv
@@ -164,4 +164,21 @@ function automatic [7:0] f();
 endfunction
 initial $t(f());
 
+initial begin
+	$t(4'b0110 ==? 4'b0z10);
+	$t(4'b0010 ==? 4'b0z10);
+	$t(4'b1110 ==? 4'b0z10);
+	$t(4'b0101 ==? 4'bzz01);
+	$t(4'b1001 ==? 4'bzz01);
+	$t(4'b1011 ==? 4'bzz01);
+	$t(4'bzzzz ==? 4'b0000);
+	$t(4'b0110 ==? 4'b0x10);
+	$t(4'b0010 ==? 4'b0x10);
+	$t(4'b1110 ==? 4'b0x10);
+	$t(4'b0101 ==? 4'bxx01);
+	$t(4'b1001 ==? 4'bxx01);
+	$t(4'b1011 ==? 4'bxx01);
+	$t(4'bxxxx ==? 4'b0000);
+end
+
 endmodule