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ESP SoC Reset sequences #2164
ESP SoC Reset sequences #2164
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Better, but still not quite right: this PR only works once per power cycle, just as OP said. However, for me pressing Rst works, too, no need to unplug.
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DebugSequence::Arm(_) => panic!("There are no ARM ESP targets."), | ||
}; | ||
let flash_size_result = session.halted_access(|sess| { | ||
// Figure out flash size from the memory map. We need a different bootloader for each size. |
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Please keep bugging me to work on this, these need to be custom flash algo functions and not sequences.
Also I don't think we need the clone
here any more, but I'm not 100% sure.
So I have found the issue, and a work around, but it's not clear to me if we can do better. The IDF application re-enables watchdogs during its application, when you Ctl+C, the application halts (stop petting the wdg) and the board resets after some period. It's possible to begin reflashing before the wdg reset if you're fast enough and reflashing works perfectly. The workaround is to pass |
…atus and soc_reset if its enabled
Builds on top of #2151
Supercededes #1965
Closes #1963.
I still notice some oddities, where the probe/dtm becomes unresponsive, particularly after flashing once. I usually then need to physically unplug the board and replug for flashing to work again. Not sure what's causing that atm, but this PR should still bring us a step closer.
Draft until all chips are supported.