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[RV64_DYNAREC] Added 66 0F D4 PADDQ opcode for vector and fixes SEW cache transform #1812

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merged 2 commits into from
Sep 10, 2024
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[RV64_DYNAREC] Added 66 0F D4 PADDQ opcode for vector and fixes SEW cache transform #1812

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f3af885
[RV64_DYNAREC] Added 66 0F D4 PADDQ opcode for vector
ksco Sep 10, 2024
8cf4444
[RV64_DYNAREC] Transform SEW cache after fpu cache
ksco Sep 10, 2024
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8 changes: 8 additions & 0 deletions src/dynarec/rv64/dynarec_rv64_660f_vector.c
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Original file line number Diff line number Diff line change
Expand Up @@ -194,6 +194,14 @@ uintptr_t dynarec64_660F_vector(dynarec_rv64_t* dyn, uintptr_t addr, uintptr_t i
VXOR_VV(q0, q0, q1, VECTOR_UNMASKED);
}
break;
case 0xD4:
INST_NAME("PADDQ Gx,Ex");
nextop = F8;
SET_ELEMENT_WIDTH(x1, VECTOR_SEW64, 1);
GETGX_vector(q0, 1, VECTOR_SEW64);
GETEX_vector(q1, 0, 0, VECTOR_SEW64);
VADD_VV(q0, q0, q1, VECTOR_UNMASKED);
break;
default:
DEFAULT_VECTOR;
}
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7 changes: 4 additions & 3 deletions src/dynarec/rv64/dynarec_rv64_helper.c
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Expand Up @@ -2437,13 +2437,14 @@ static void sewTransform(dynarec_rv64_t* dyn, int ninst, int s1)
vector_vsetvl_emul1(dyn, ninst, s1, dyn->insts[jmp].vector_sew);
}

void CacheTransform(dynarec_rv64_t* dyn, int ninst, int cacheupd, int s1, int s2, int s3) {
if (cacheupd & 4)
sewTransform(dyn, ninst, s1);
void CacheTransform(dynarec_rv64_t* dyn, int ninst, int cacheupd, int s1, int s2, int s3)
{
if (cacheupd & 2)
fpuCacheTransform(dyn, ninst, s1, s2, s3);
if (cacheupd & 1)
flagsCacheTransform(dyn, ninst, s1);
if (cacheupd & 4)
sewTransform(dyn, ninst, s1);
}


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