[rv_dm,lc_ctrl,darjeeling] Convert DMI to real TL-UL interface

Change DMI implementation to TL-UL, and rework rv_dm and lc_ctrl to
match. Ensure rv_dm continues to respond with zeroes when the DM is not
present / inaccessible.

Rewire JTAG to place lc_ctrl and rv_dm on the same TAP, and use
dedicated DIOs for JTAG at the top. Generate a RAL model for the new
TL-UL interconnect, and use it in DV. Also fix up macro names in
software for the new lc_ctrl named register interfaces. Finally,
eliminate the TAP and DFT straps and related tests, as they are now
unused.

rv_dm is located at address 0 in the map. This is required by the RISC-V
Debug specification, as it is the first Debug Module. If other Debug
Modules are to be used, they could be placed elsewhere on the TL-UL
network, and the nextdm CSR for the first DM would point to the base
address of the next.

lc_ctrl is currently located at 0x20000 in the map. This may be changed
to match data sheet and/or flexibility preferences. This address
currently must be hard-coded (or chained to the number of DMI abits), as
there is no method specified for probing this address. Only the IDCODE
and what can be read from the DTMCS register are currently usable keys
for finding out the DMI addresses. Alternative mechanisms are left for
future discussions.

Signed-off-by: Alexander Williams <awill@opentitan.org>
Co-authored-by: Michael Schaffner <msf@opentitan.org>

hw/ip/lc_ctrl/data/lc_ctrl.hjson

@@ -25,7 +25,8 @@
     {clock: "clk_kmac_i", reset: "rst_kmac_ni"}
   ]
   bus_interfaces: [
-    { protocol: "tlul", direction: "device", name: "regs" }
+    { protocol: "tlul", direction: "device", name: "regs" },
+    { protocol: "tlul", direction: "device", name: "dmi"  }
   ],
   scan: "false", // Enable `scanmode_i` port
   scan_reset: "false", // Enable `scan_rst_ni` port
@@ -191,25 +192,6 @@
   /////////////////////////////
 
   inter_signal_list: [
-    // TL-UL-based DMI
-    { struct:  "tl_h2d"
-      package: "tlul_pkg"
-      type:    "uni"
-      name:    "dmi_tl_h2d"
-      act:     "rcv"
-      desc:    '''
-               TL-UL-based DMI request input port
-               '''
-    }
-    { struct:  "tl_d2h"
-      package: "tlul_pkg"
-      type:    "uni"
-      name:    "dmi_tl_d2h"
-      act:     "req"
-      desc:    '''
-               TL-UL-based DMI response output port
-               '''
-    }
     // Escalation inputs from alert handler
     { struct:  "esc_tx"
       type:    "uni"
@@ -1279,5 +1261,18 @@
         }
       }
     ]
+    // Debug bus attachment
+    dmi: [
+      { window: {
+          name: "dmi"
+          // 0x0 ... 0x400 word addresses are allocated here.
+          items: "1024"
+          swaccess: "rw",
+          data-intg-passthru: "true",
+          byte-write: "false",
+          desc: '''Access window to lc_ctrl CSRs and .'''
+        }
+      },
+    ]
   }
 }

hw/ip/lc_ctrl/dv/sva/lc_ctrl_bind.sv

@@ -18,8 +18,8 @@ module lc_ctrl_bind;
   ) tlul_assert_device_dmi (
     .clk_i,
     .rst_ni,
-    .h2d  (dmi_tl_h2d_i),
-    .d2h  (dmi_tl_d2h_o)
+    .h2d  (dmi_tl_i),
+    .d2h  (dmi_tl_o)
   );
 
   bind lc_ctrl lc_ctrl_regs_csr_assert_fpv lc_ctrl_regs_csr_assert (

hw/ip/lc_ctrl/dv/tb.sv

@@ -141,8 +141,8 @@ module tb;
     .alert_rx_i(alert_rx),
     .alert_tx_o(alert_tx),
 
-    .dmi_tl_h2d_i(dmi_tl_h2d),
-    .dmi_tl_d2h_o(dmi_tl_d2h),
+    .dmi_tl_i(dmi_tl_h2d),
+    .dmi_tl_o(dmi_tl_d2h),
 
     .esc_scrap_state0_tx_i(esc_scrap_state0_if.esc_tx),
     .esc_scrap_state0_rx_o(esc_scrap_state0_if.esc_rx),

hw/ip/lc_ctrl/lc_ctrl.core

@@ -23,6 +23,7 @@ filesets:
       - lowrisc:ip:jtag_pkg
     files:
       - rtl/lc_ctrl_regs_reg_top.sv
+      - rtl/lc_ctrl_dmi_reg_top.sv
       - rtl/lc_ctrl_state_decode.sv
       - rtl/lc_ctrl_state_transition.sv
       - rtl/lc_ctrl_signal_decode.sv

hw/ip/lc_ctrl/rtl/lc_ctrl.sv

@@ -35,8 +35,8 @@ module lc_ctrl
   input  tlul_pkg::tl_h2d_t                          regs_tl_i,
   output tlul_pkg::tl_d2h_t                          regs_tl_o,
   // TL-UL-based DMI
-  input  tlul_pkg::tl_h2d_t                          dmi_tl_h2d_i,
-  output tlul_pkg::tl_d2h_t                          dmi_tl_d2h_o,
+  input  tlul_pkg::tl_h2d_t                          dmi_tl_i,
+  output tlul_pkg::tl_d2h_t                          dmi_tl_o,
   // Alert outputs.
   input  prim_alert_pkg::alert_rx_t [NumAlerts-1:0]  alert_rx_i,
   output prim_alert_pkg::alert_tx_t [NumAlerts-1:0]  alert_tx_o,
@@ -153,8 +153,8 @@ module lc_ctrl
   lc_ctrl_regs_reg_top u_reg_dmi (
     .clk_i,
     .rst_ni,
-    .tl_i      ( dmi_tl_h2d_i                ),
-    .tl_o      ( dmi_tl_d2h_o                ),
+    .tl_i      ( dmi_tl_i                    ),
+    .tl_o      ( dmi_tl_o                    ),
     .reg2hw    ( dmi_reg2hw                  ),
     .hw2reg    ( dmi_hw2reg                  ),
     // SEC_CM: BUS.INTEGRITY
@@ -660,6 +660,7 @@ module lc_ctrl
   ////////////////
 
   `ASSERT_KNOWN(RegsTlOKnown,           regs_tl_o                  )
+  `ASSERT_KNOWN(DmiTlOKnown,            dmi_tl_o                   )
   `ASSERT_KNOWN(AlertTxKnown_A,         alert_tx_o                 )
   `ASSERT_KNOWN(PwrLcKnown_A,           pwr_lc_o                   )
   `ASSERT_KNOWN(LcOtpProgramKnown_A,    lc_otp_program_o           )
@@ -704,5 +705,5 @@ module lc_ctrl
 
   // Alert assertions for reg_we onehot check
   `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(RegsWeOnehotCheck_A, u_reg_regs, alert_tx_o[2])
-  `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(DmiRegWeOnehotCheck_A, u_reg_dmi, alert_tx_o[2], 0)
+  `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(DmiWeOnehotCheck_A, u_reg_dmi, alert_tx_o[2], 0)
 endmodule : lc_ctrl

hw/ip/lc_ctrl/rtl/lc_ctrl_dmi_reg_top.sv

@@ -0,0 +1,66 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Register Top module auto-generated by `reggen`
+
+`include "prim_assert.sv"
+
+module lc_ctrl_dmi_reg_top (
+  input clk_i,
+  input rst_ni,
+  input  tlul_pkg::tl_h2d_t tl_i,
+  output tlul_pkg::tl_d2h_t tl_o,
+
+  // Output port for window
+  output tlul_pkg::tl_h2d_t tl_win_o,
+  input  tlul_pkg::tl_d2h_t tl_win_i,
+
+  // To HW
+
+  // Integrity check errors
+  output logic intg_err_o,
+
+  // Config
+  input devmode_i // If 1, explicit error return for unmapped register access
+);
+
+  import lc_ctrl_reg_pkg::* ;
+
+
+  // Add an unloaded flop to make use of clock / reset
+  // This is done to specifically address lint complaints of unused clocks/resets
+  // Since the flop is unloaded it will be removed during synthesis
+  logic unused_reg;
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      unused_reg <= '0;
+    end else begin
+      unused_reg <= tl_i.a_valid;
+    end
+  end
+
+
+
+  // Since there are no registers in this block, commands are routed through to windows which
+  // can report their own integrity errors.
+  assign intg_err_o = 1'b0;
+
+  // outgoing integrity generation
+  tlul_pkg::tl_d2h_t tl_o_pre;
+  tlul_rsp_intg_gen #(
+    .EnableRspIntgGen(1),
+    .EnableDataIntgGen(0)
+  ) u_rsp_intg_gen (
+    .tl_i(tl_o_pre),
+    .tl_o(tl_o)
+  );
+
+  assign tl_win_o = tl_i;
+  assign tl_o_pre = tl_win_i;
+
+  // Unused signal tieoff
+  // devmode_i is not used if there are no registers
+  logic unused_devmode;
+  assign unused_devmode = ^devmode_i;
+endmodule

hw/ip/lc_ctrl/rtl/lc_ctrl_reg_pkg.sv

@@ -22,6 +22,7 @@ package lc_ctrl_reg_pkg;
 
   // Address widths within the block
   parameter int RegsAw = 8;
+  parameter int DmiAw = 12;
 
   ///////////////////////////////////////////////
   // Typedefs for registers for regs interface //
@@ -375,4 +376,9 @@ package lc_ctrl_reg_pkg;
     4'b 1111  // index[34] LC_CTRL_MANUF_STATE_7
   };
 
+  // Window parameters for dmi interface
+  parameter logic [DmiAw-1:0] LC_CTRL_DMI_OFFSET = 12'h 0;
+  parameter int unsigned      LC_CTRL_DMI_SIZE   = 'h 1000;
+  parameter int unsigned      LC_CTRL_DMI_IDX    = 0;
+
 endpackage

hw/ip/rv_dm/data/rv_dm.hjson

@@ -27,6 +27,7 @@
     { protocol: "tlul", direction: "host",   name: "sba" }
     { protocol: "tlul", direction: "device", name: "regs" }
     { protocol: "tlul", direction: "device", name: "mem" }
+    { protocol: "tlul", direction: "device", name: "dbg" }
   ],
   scan: "true", // Enable `scanmode_i` port
   scan_reset: "false", // Enable `scan_rst_ni` port
@@ -73,27 +74,7 @@
                32bit word address of the next debug module.
                Set to 0x0 if this is the last debug module in the chain.
                '''
-    }
-    {
-      struct:  "tl_h2d"
-      package: "tlul_pkg"
-      type:    "uni"
-      name:    "dmi_tl_h2d"
-      act:     "rcv"
-      desc:    '''
-               TLUL-based DMI request input port
-               '''
-    }
-    {
-      struct:  "tl_d2h"
-      package: "tlul_pkg"
-      type:    "uni"
-      name:    "dmi_tl_d2h"
-      act:     "req"
-      desc:    '''
-               TLUL-based DMI response output port
-               '''
-    }
+    },
     { struct:  "lc_tx"
       type:    "uni"
       name:    "lc_hw_debug_en"
@@ -360,5 +341,18 @@
         }
       },
     ]
+    // Debug bus attachment
+    dbg: [
+      { window: {
+          name: "dbg"
+          // 0x0 ... 0x40 word addresses are allocated here.
+          items: "128"
+          swaccess: "rw",
+          data-intg-passthru: "true",
+          byte-write: "false",
+          desc: '''Access window to DM CSRs.'''
+        }
+      },
+    ]
   }
 }

hw/ip/rv_dm/dv/sva/rv_dm_bind.sv

@@ -9,8 +9,8 @@ module rv_dm_bind;
   ) tlul_assert_device_dmi (
     .clk_i,
     .rst_ni,
-    .h2d  (dmi_tl_h2d_i),
-    .d2h  (dmi_tl_d2h_o)
+    .h2d  (dbg_tl_d_i),
+    .d2h  (dbg_tl_d_o)
   );
 
   bind rv_dm tlul_assert #(

hw/ip/rv_dm/dv/tb.sv

@@ -27,8 +27,8 @@ module tb;
   rv_dm_if rv_dm_if(.clk(clk), .rst_n(rst_n));
 
   // Used for JTAG DTM connections via TL-UL.
-  tlul_pkg::tl_h2d_t dmi_tl_h2d;
-  tlul_pkg::tl_d2h_t dmi_tl_d2h;
+  tlul_pkg::tl_h2d_t dbg_tl_h2d;
+  tlul_pkg::tl_d2h_t dbg_tl_d2h;
 
   `DV_ALERT_IF_CONNECT()
 
@@ -43,8 +43,8 @@ module tb;
     .jtag_o      ({jtag_if.tdo, jtag_tdo_oe}),
     .scan_rst_ni (rv_dm_if.scan_rst_n),
     .scanmode_i  (rv_dm_if.scanmode),
-    .tl_h2d_o    (dmi_tl_h2d),
-    .tl_d2h_i    (dmi_tl_d2h)
+    .tl_h2d_o    (dbg_tl_h2d),
+    .tl_d2h_i    (dbg_tl_d2h)
   );
 
   // dut
@@ -74,8 +74,8 @@ module tb;
     .sba_tl_h_o           (sba_tl_if.h2d),
     .sba_tl_h_i           (sba_tl_if.d2h),
 
-    .dmi_tl_h2d_i         (dmi_tl_h2d),
-    .dmi_tl_d2h_o         (dmi_tl_d2h),
+    .dbg_tl_d_i           (dbg_tl_h2d),
+    .dbg_tl_d_o           (dbg_tl_d2h),
 
     .alert_rx_i           (alert_rx),
     .alert_tx_o           (alert_tx)

hw/ip/rv_dm/rtl/rv_dm.sv

@@ -53,8 +53,8 @@ module rv_dm
   output prim_alert_pkg::alert_tx_t [NumAlerts-1:0] alert_tx_o,
 
   // TL-UL-based DMI
-  input  tlul_pkg::tl_h2d_t dmi_tl_h2d_i,
-  output tlul_pkg::tl_d2h_t dmi_tl_d2h_o
+  input  tlul_pkg::tl_h2d_t dbg_tl_d_i,
+  output tlul_pkg::tl_d2h_t dbg_tl_d_o
 );
 
   ///////////////////////////
@@ -292,7 +292,18 @@ module rv_dm
 
   // Bound-in DPI module replaces the TAP and TL-UL DMI
 `ifndef DMIDirectTAP
-  assign dbg_intg_error = 1'b0;
+  tlul_pkg::tl_h2d_t dbg_tl_h2d_win;
+  tlul_pkg::tl_d2h_t dbg_tl_d2h_win;
+  rv_dm_dbg_reg_top u_rv_dm_dbg_reg_top (
+    .clk_i,
+    .rst_ni,
+    .tl_i      (dbg_tl_d_i),
+    .tl_o      (dbg_tl_d_o),
+    .tl_win_o  (dbg_tl_h2d_win),
+    .tl_win_i  (dbg_tl_d2h_win),
+    .intg_err_o(dbg_intg_error),
+    .devmode_i (1'b1)
+  );
 
   rv_dm_dmi_gate #(
     .SecVolatileRawUnlockEn(SecVolatileRawUnlockEn)
@@ -304,8 +315,8 @@ module rv_dm
     .lc_hw_debug_en_i,
     .lc_check_byp_en_i,
     .lc_escalate_en_i,
-    .dbg_tl_h2d_win_i(               dmi_tl_h2d_i),
-    .dbg_tl_d2h_win_o(               dmi_tl_d2h_o),
+    .dbg_tl_h2d_win_i(               dbg_tl_h2d_win),
+    .dbg_tl_d2h_win_o(               dbg_tl_d2h_win),
     .dmi_req_valid_o(                dmi_req_valid),
     .dmi_req_ready_i(                dmi_req_ready),
     .dmi_req_o(                      dmi_req),
@@ -441,8 +452,8 @@ module rv_dm
   `ASSERT_KNOWN(TlSbaAValidKnown_A, sba_tl_h_o.a_valid)
   `ASSERT_KNOWN(TlSbaDReadyKnown_A, sba_tl_h_o.d_ready)
 
-  `ASSERT_KNOWN(TlDmiDValidKnown_A, dmi_tl_d2h_o.d_valid)
-  `ASSERT_KNOWN(TlDmiAReadyKnown_A, dmi_tl_d2h_o.a_ready)
+  `ASSERT_KNOWN(TlDbgDValidKnown_A, dbg_tl_d_o.d_valid)
+  `ASSERT_KNOWN(TlDbgAReadyKnown_A, dbg_tl_d_o.a_ready)
 
   `ASSERT_KNOWN(NdmresetOKnown_A, ndmreset_req_o)
   `ASSERT_KNOWN(DmactiveOKnown_A, dmactive_o)