GitHub - qmn/riscv-invicta: A simple RISC-V core, described with Verilog

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A simple RISC-V core, described with Verilog

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riscv-invicta
Author: Quan Nguyen - [first][last]@berkeley.edu


                   O o o
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(Image source: Wikipedia)


riscv-invicta is a simple 32-bit, one-stage, in-order RISC-V core.