Conversation
Controlled Swap between two registers of bit length of size one and controlled swap between two registers of bit lenght size n, n>1.
|
@ncrubin FYI, Multi Target CSWAP already exists as a cirq gate, but I understand if we want to have it as a bloq as well given the importance. |
| def pretty_name(self) -> str: | ||
| return "CSWAP" | ||
|
|
||
| def build_composite_bloq( |
There was a problem hiding this comment.
have you tried actually decomposing the bloq? That's when it will check the code to see if it results in a well-formed composite bloq.
bloq = CMultiSWAP(...)
cbloq = bloq.decompose_bloq()
from cirq_qubitization.jupyter_tools import show_bloq
show_bloq(cbloq)There was a problem hiding this comment.
I haven't yet..but I will tomorrow!
| return "CSWAP" | ||
|
|
||
| def build_composite_bloq( | ||
| self, bb: 'CompositeBloqBuilder', *, cntrl_and_targets: NDArray[Soquet] |
There was a problem hiding this comment.
The arguments should match the registers, so you should have three arguments (following the bb and *) named ctrl, reg_x, and reg_y
| FancyRegister('ctrl', 1, wireshape=(1,)), | ||
| FancyRegister('reg_x', self.reg_length, wireshape=(1,)), | ||
| FancyRegister('reg_y', self.reg_length, wireshape=(1,)), |
There was a problem hiding this comment.
wireshape=(1,) is equivalent to "list of length 1", which can have a use (usually when writing generic code that works for a list of any size) but is probably inappropriate here. wireshape=tuple() (which is the default argument, so you can just not put it) is analogous to "the item itself -- not in a list".
| returned_x.append(out_reg_x) | ||
| returned_y.append(out_reg_y) |
There was a problem hiding this comment.
this style is good for making it clear that the output quantum variables are distinct from the input ones. You can be more concise by just overwriting the original array values
ctrl, reg_x[n_idx], reg_y[n_idx] = bb.add(...)
yup just wanted a simple example to play around with making bloqs. |
Controlled Swap between two registers of bit length of size one and controlled swap between two registers of bit lenght size n, n>1.