Can gates in the circuit file be out of order?

[95-martin-orion]

I'm working on a generator for qsim circuits, and for certain gates that qsim does not support it decomposes the gate into a sequence that qsim does support. If there are other gates running at the same time, this can create out-of-order gates in the file, e.g.:

# one input gate
0 rxy 0 0.5 0.25
1 rz 0 0.5
# another input gate
0 cp 1 2 0.75

Is this allowed in qsim or not? Either way, can we update input_format.md to clarify this for users?

(I have no preference for whether we should support this or not - if it's currently not allowed, I can refactor my generator code.)

[sergeisakov]

It depends. Your example will work. However, the following examples will not work:

# one input gate
1 rz 0 0.5
0 rxy 0 0.5 0.25
# another input gate
0 cp 1 2 0.75

or

0 rxy 0 0.5 0.25
2 rz 0 0.5
0 cp 1 2 0.75
1 cz 0 1

That is gates acting on the same qubits must be in ascending order of time. This can be fixed by sorting gates or as you suggested, we can update input_format.md to clarify this.