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drm/v3d: Fix GPU reset issues on the Raspberry Pi 5 #6692

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Merged
merged 7 commits into from
Mar 7, 2025
Merged

drm/v3d: Fix GPU reset issues on the Raspberry Pi 5 #6692

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56f37a0
drm/v3d: Add clock handling
lategoodbye Feb 1, 2025
5f23f40
drm/v3d: Don't run jobs that have errors flagged in its fence
mairacanal Feb 22, 2025
2ecfbc0
drm/v3d: Set job pointer to NULL when the job's fence has an error
mairacanal Feb 22, 2025
9413b73
drm/v3d: Associate a V3D tech revision to all supported devices
mairacanal Feb 25, 2025
6c84e13
dt-bindings: gpu: v3d: Add SMS to the registers' list
mairacanal Feb 22, 2025
19aae53
drm/v3d: Use V3D_SMS registers for power on/off and reset on V3D 7.x
mairacanal Feb 22, 2025
785784e
dts: bcm2712: Add V3D_SMS register
mairacanal Feb 28, 2025
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6 changes: 4 additions & 2 deletions Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -27,14 +27,16 @@ properties:
- description: core0 register (required)
- description: GCA cache controller register (if GCA controller present)
- description: bridge register (if no external reset controller)
- description: SMS register (if SMS controller present)
minItems: 2

reg-names:
items:
- const: hub
- const: core0
- enum: [ bridge, gca ]
- enum: [ bridge, gca ]
- enum: [ bridge, gca, sms ]
- enum: [ bridge, gca, sms ]
- enum: [ bridge, gca, sms ]
minItems: 2

interrupts:
Expand Down
5 changes: 3 additions & 2 deletions arch/arm64/boot/dts/broadcom/bcm2712.dtsi
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Expand Up @@ -1222,8 +1222,9 @@
v3d: v3d@2000000 {
compatible = "brcm,2712-v3d";
reg = <0x10 0x02000000 0x0 0x4000>,
<0x10 0x02008000 0x0 0x6000>;
reg-names = "hub", "core0";
<0x10 0x02008000 0x0 0x6000>,
<0x10 0x02030800 0x0 0x0700>;
reg-names = "hub", "core0", "sms";

power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
resets = <&pm BCM2835_RESET_V3D>;
Expand Down
128 changes: 64 additions & 64 deletions drivers/gpu/drm/v3d/v3d_debugfs.c
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Original file line number Diff line number Diff line change
Expand Up @@ -22,74 +22,74 @@ struct v3d_reg_def {
};

static const struct v3d_reg_def v3d_hub_reg_defs[] = {
REGDEF(33, 42, V3D_HUB_AXICFG),
REGDEF(33, 71, V3D_HUB_UIFCFG),
REGDEF(33, 71, V3D_HUB_IDENT0),
REGDEF(33, 71, V3D_HUB_IDENT1),
REGDEF(33, 71, V3D_HUB_IDENT2),
REGDEF(33, 71, V3D_HUB_IDENT3),
REGDEF(33, 71, V3D_HUB_INT_STS),
REGDEF(33, 71, V3D_HUB_INT_MSK_STS),

REGDEF(33, 71, V3D_MMU_CTL),
REGDEF(33, 71, V3D_MMU_VIO_ADDR),
REGDEF(33, 71, V3D_MMU_VIO_ID),
REGDEF(33, 71, V3D_MMU_DEBUG_INFO),

REGDEF(71, 71, V3D_V7_GMP_STATUS),
REGDEF(71, 71, V3D_V7_GMP_CFG),
REGDEF(71, 71, V3D_V7_GMP_VIO_ADDR),
REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_HUB_AXICFG),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_UIFCFG),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT0),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT1),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT2),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT3),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_STS),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_MSK_STS),

REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_CTL),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ADDR),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ID),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_DEBUG_INFO),

REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_GMP_STATUS),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_GMP_CFG),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_GMP_VIO_ADDR),
};

static const struct v3d_reg_def v3d_gca_reg_defs[] = {
REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN),
REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN_ACK),
REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN),
REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN_ACK),
};

static const struct v3d_reg_def v3d_core_reg_defs[] = {
REGDEF(33, 71, V3D_CTL_IDENT0),
REGDEF(33, 71, V3D_CTL_IDENT1),
REGDEF(33, 71, V3D_CTL_IDENT2),
REGDEF(33, 71, V3D_CTL_MISCCFG),
REGDEF(33, 71, V3D_CTL_INT_STS),
REGDEF(33, 71, V3D_CTL_INT_MSK_STS),
REGDEF(33, 71, V3D_CLE_CT0CS),
REGDEF(33, 71, V3D_CLE_CT0CA),
REGDEF(33, 71, V3D_CLE_CT0EA),
REGDEF(33, 71, V3D_CLE_CT1CS),
REGDEF(33, 71, V3D_CLE_CT1CA),
REGDEF(33, 71, V3D_CLE_CT1EA),

REGDEF(33, 71, V3D_PTB_BPCA),
REGDEF(33, 71, V3D_PTB_BPCS),

REGDEF(33, 41, V3D_GMP_STATUS),
REGDEF(33, 41, V3D_GMP_CFG),
REGDEF(33, 41, V3D_GMP_VIO_ADDR),

REGDEF(33, 71, V3D_ERR_FDBGO),
REGDEF(33, 71, V3D_ERR_FDBGB),
REGDEF(33, 71, V3D_ERR_FDBGS),
REGDEF(33, 71, V3D_ERR_STAT),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT0),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT1),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT2),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_MISCCFG),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_STS),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_MSK_STS),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CS),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CA),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0EA),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CS),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CA),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1EA),

REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCA),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCS),

REGDEF(V3D_GEN_33, V3D_GEN_41, V3D_GMP_STATUS),
REGDEF(V3D_GEN_33, V3D_GEN_41, V3D_GMP_CFG),
REGDEF(V3D_GEN_33, V3D_GEN_41, V3D_GMP_VIO_ADDR),

REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGO),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGB),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGS),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_STAT),
};

static const struct v3d_reg_def v3d_csd_reg_defs[] = {
REGDEF(41, 71, V3D_CSD_STATUS),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG0),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG1),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG2),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG3),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG4),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG5),
REGDEF(41, 41, V3D_CSD_CURRENT_CFG6),
REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG0),
REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG1),
REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG2),
REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG3),
REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG4),
REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG5),
REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG6),
REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG7),
REGDEF(V3D_GEN_41, V3D_GEN_71, V3D_CSD_STATUS),
REGDEF(V3D_GEN_41, V3D_GEN_41, V3D_CSD_CURRENT_CFG0),
REGDEF(V3D_GEN_41, V3D_GEN_41, V3D_CSD_CURRENT_CFG1),
REGDEF(V3D_GEN_41, V3D_GEN_41, V3D_CSD_CURRENT_CFG2),
REGDEF(V3D_GEN_41, V3D_GEN_41, V3D_CSD_CURRENT_CFG3),
REGDEF(V3D_GEN_41, V3D_GEN_41, V3D_CSD_CURRENT_CFG4),
REGDEF(V3D_GEN_41, V3D_GEN_41, V3D_CSD_CURRENT_CFG5),
REGDEF(V3D_GEN_41, V3D_GEN_41, V3D_CSD_CURRENT_CFG6),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG0),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG1),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG2),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG3),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG4),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG5),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG6),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG7),
};

static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
Expand Down Expand Up @@ -165,7 +165,7 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU));
seq_printf(m, "TFU: %s\n",
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU));
if (v3d->ver <= 42) {
if (v3d->ver <= V3D_GEN_42) {
seq_printf(m, "TSY: %s\n",
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
}
Expand Down Expand Up @@ -197,11 +197,11 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
seq_printf(m, " QPUs: %d\n", nslc * qups);
seq_printf(m, " Semaphores: %d\n",
V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
if (v3d->ver <= 42) {
if (v3d->ver <= V3D_GEN_42) {
seq_printf(m, " BCG int: %d\n",
(ident2 & V3D_IDENT2_BCG_INT) != 0);
}
if (v3d->ver < 40) {
if (v3d->ver < V3D_GEN_41) {
seq_printf(m, " Override TMU: %d\n",
(misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
}
Expand Down Expand Up @@ -311,8 +311,8 @@ static int v3d_measure_clock(struct seq_file *m, void *unused)
int core = 0;
int measure_ms = 1000;

if (v3d->ver >= 40) {
int cycle_count_reg = v3d->ver < 71 ?
if (v3d->ver >= V3D_GEN_41) {
int cycle_count_reg = v3d->ver < V3D_GEN_71 ?
V3D_PCTR_CYCLE_COUNT : V3D_V7_PCTR_CYCLE_COUNT;
V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
V3D_SET_FIELD(cycle_count_reg,
Expand Down
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