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documentationImprovements or additions to documentationImprovements or additions to documentationrp2040Concerning the RP2040 chipConcerning the RP2040 chip
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Table 280 (PHASE Register) in Section 2.17.8 (List of ROSC Registers) of RP2040 datasheet reads:
11:4 | PASSWD | set to 0xaa0, any other value enables the output with shift=0 | RW | 0x00
Obviously, the constant 0xaa0 does not fit into the range of 8 bits (11:4). Maybe the constant should read 0xaa? Or 0xa0?
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documentationImprovements or additions to documentationImprovements or additions to documentationrp2040Concerning the RP2040 chipConcerning the RP2040 chip