soc: update IBUS and IOPMP configurations

redchenjs · May 23, 2023 · 987b9de · 987b9de
1 parent 84359fd
commit 987b9de
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Showing 7 changed files with 63 additions and 59 deletions.
diff --git a/sdk/projects/apps/wujian100_open-driver/pmp.c b/sdk/projects/apps/wujian100_open-driver/pmp.c
@@ -97,8 +97,8 @@ void pmp_init(void)
     PMP_CTRL_0_REG = PMP_RESET_BIT;
     PMP_CTRL_1_REG = PMP_RESET_BIT;
 
-    PMP_CONF_0_0_BASE_REG = 0x00000000;
-    PMP_CONF_0_0_MASK_REG = 0x00000000;
+    PMP_CONF_0_0_BASE_REG = 0x20000000; // IRAM-APP1
+    PMP_CONF_0_0_MASK_REG = 0xFFFF0000; // 0x20000000 - 0x2000FFFF
     PMP_CONF_0_1_BASE_REG = 0x00000000;
     PMP_CONF_0_1_MASK_REG = 0x00000000;
     PMP_CONF_0_2_BASE_REG = 0x00000000;
@@ -114,25 +114,25 @@ void pmp_init(void)
     PMP_CONF_0_7_BASE_REG = 0x00000000;
     PMP_CONF_0_7_MASK_REG = 0x00000000;
 
-    PMP_CONF_1_0_BASE_REG = 0x20000000; // IRAM-APP1
-    PMP_CONF_1_0_MASK_REG = 0xFFFF0000; // 0x20000000 - 0x2000FFFF
-    PMP_CONF_1_1_BASE_REG = 0x20020000; // SRAM-APP1
-    PMP_CONF_1_1_MASK_REG = 0xFFFF0000; // 0x20020000 - 0x2002FFFF
-    PMP_CONF_1_2_BASE_REG = 0x40010000; // MAILBOX_0
-    PMP_CONF_1_2_MASK_REG = 0xFFFF0000; // 0x40010000 - 0x4001FFFF
-    PMP_CONF_1_3_BASE_REG = 0x40020000; // MAILBOX_1
-    PMP_CONF_1_3_MASK_REG = 0xFFFF0000; // 0x40020000 - 0x4002FFFF
-    PMP_CONF_1_4_BASE_REG = 0x60000000; // TIM_2
-    PMP_CONF_1_4_MASK_REG = 0xFFFFFFE0; // 0x60000000 - 0x6000001F
-    PMP_CONF_1_5_BASE_REG = 0x60018000; // GPIO
-    PMP_CONF_1_5_MASK_REG = 0xFFFFF000; // 0x60018000 - 0x60018FFF
-    PMP_CONF_1_6_BASE_REG = 0x60028000; // USI_1
-    PMP_CONF_1_6_MASK_REG = 0xFFFFF000; // 0x60028000 - 0x60028FFF
+    PMP_CONF_1_0_BASE_REG = 0x20020000; // SRAM-APP1
+    PMP_CONF_1_0_MASK_REG = 0xFFFF0000; // 0x20020000 - 0x2002FFFF
+    PMP_CONF_1_1_BASE_REG = 0x40010000; // MAILBOX_0
+    PMP_CONF_1_1_MASK_REG = 0xFFFF0000; // 0x40010000 - 0x4001FFFF
+    PMP_CONF_1_2_BASE_REG = 0x40020000; // MAILBOX_1
+    PMP_CONF_1_2_MASK_REG = 0xFFFF0000; // 0x40020000 - 0x4002FFFF
+    PMP_CONF_1_3_BASE_REG = 0x60000000; // TIM_2
+    PMP_CONF_1_3_MASK_REG = 0xFFFFFFE0; // 0x60000000 - 0x6000001F
+    PMP_CONF_1_4_BASE_REG = 0x60018000; // GPIO
+    PMP_CONF_1_4_MASK_REG = 0xFFFFF000; // 0x60018000 - 0x60018FFF
+    PMP_CONF_1_5_BASE_REG = 0x60028000; // USI_1
+    PMP_CONF_1_5_MASK_REG = 0xFFFFF000; // 0x60028000 - 0x60028FFF
+    PMP_CONF_1_6_BASE_REG = 0x00000000;
+    PMP_CONF_1_6_MASK_REG = 0x00000000;
     PMP_CONF_1_7_BASE_REG = 0x00000000;
     PMP_CONF_1_7_MASK_REG = 0x00000000;
 
-    PMP_CTRL_0_REG = 0x00;
-    PMP_CTRL_1_REG = 0x7f;
+    PMP_CTRL_0_REG = 0x01;
+    PMP_CTRL_1_REG = 0x3f;
 }
 
 bool pmp_get_err(uint8_t idx)

diff --git a/soc/E902_20191018.v b/soc/E902_20191018.v
@@ -771,8 +771,8 @@ input           lsu_bmu_store_error;
 input   [31:0]  lsu_bmu_wdata;                   
 input           lsu_bmu_wfd1;                    
 input           lsu_bmu_write;                   
-input   [11:0]  pad_bmu_iahbl_base;              
-input   [11:0]  pad_bmu_iahbl_mask;              
+input   [15:0]  pad_bmu_iahbl_base;              
+input   [15:0]  pad_bmu_iahbl_mask;              
 input           pmp_bmu_dbus_acc_deny;           
 input           tcipif_bmu_dbus_acc_err;         
 input   [31:0]  tcipif_bmu_dbus_data;            
@@ -908,8 +908,8 @@ wire            lsu_bmu_wfd1;
 wire            lsu_bmu_write;                   
 wire            lsu_inst_lrw;                    
 wire            lsu_inst_norm;                   
-wire    [11:0]  pad_bmu_iahbl_base;              
-wire    [11:0]  pad_bmu_iahbl_mask;              
+wire    [15:0]  pad_bmu_iahbl_base;              
+wire    [15:0]  pad_bmu_iahbl_mask;              
 wire            pmp_bmu_dbus_acc_deny;           
 wire            sahbl_req;                       
 wire            sahbl_vld;                       
@@ -932,7 +932,7 @@ assign lsu_inst_lrw  = lsu_bmu_req & !lsu_bmu_prot[0];
 assign dahbl_hit     = 1'b0;
 assign dahbl_hit_ff  = 1'b0;
 assign dahbl_hit_upd = 1'b0;
-assign iahbl_hit = ((lsu_bmu_addr[31:20] & pad_bmu_iahbl_mask[11:0]) == pad_bmu_iahbl_base[11:0]);
+assign iahbl_hit = ((lsu_bmu_addr[31:16] & pad_bmu_iahbl_mask[15:0]) == pad_bmu_iahbl_base[15:0]);
 assign iahbl_lrw_hit = iahbl_hit;
 assign iahbl_norm_hit_upd = (iahbl_norm_hit_ff ^ iahbl_hit) & lsu_inst_norm;
 always @(posedge deny_clk or negedge cpurst_b)
@@ -1241,8 +1241,8 @@ input   [3 :0]  ifu_bmu_prot;
 input           ifu_bmu_req;                
 input           ifu_bmu_wfd1;               
 input           iu_bmu_vec_redirect;        
-input   [11:0]  pad_bmu_iahbl_base;         
-input   [11:0]  pad_bmu_iahbl_mask;         
+input   [15:0]  pad_bmu_iahbl_base;         
+input   [15:0]  pad_bmu_iahbl_mask;         
 input           pmp_bmu_ibus_acc_deny;      
 input           tcipif_bmu_ibus_acc_err;    
 input   [31:0]  tcipif_bmu_ibus_data;       
@@ -1336,8 +1336,8 @@ wire    [3 :0]  ifu_bmu_prot;
 wire            ifu_bmu_req;                
 wire            ifu_bmu_wfd1;               
 wire            iu_bmu_vec_redirect;        
-wire    [11:0]  pad_bmu_iahbl_base;         
-wire    [11:0]  pad_bmu_iahbl_mask;         
+wire    [15:0]  pad_bmu_iahbl_base;         
+wire    [15:0]  pad_bmu_iahbl_mask;         
 wire            pmp_bmu_ibus_acc_deny;      
 wire            tcipif_bmu_ibus_acc_err;    
 wire    [31:0]  tcipif_bmu_ibus_data;       
@@ -1348,7 +1348,7 @@ wire            tcipif_data_vld;
 wire            tcipif_hit;                 
 wire            tcipif_hit_upd;             
 parameter TCIPIF_BASE = 4'b1110;
-assign iahbl_hit = ((ifu_bmu_addr[31:20] & pad_bmu_iahbl_mask[11:0]) == pad_bmu_iahbl_base[11:0]);
+assign iahbl_hit = ((ifu_bmu_addr[31:16] & pad_bmu_iahbl_mask[15:0]) == pad_bmu_iahbl_base[15:0]);
 assign iahbl_hit_upd = (iahbl_hit_ff ^ iahbl_hit) & ifu_bmu_req & ifu_bmu_idle;
 always @(posedge deny_clk or negedge cpurst_b)
 begin
@@ -1602,8 +1602,8 @@ input           lsu_bmu_store_error;
 input   [31:0]  lsu_bmu_wdata;                   
 input           lsu_bmu_wfd1;                    
 input           lsu_bmu_write;                   
-input   [11:0]  pad_bmu_iahbl_base;              
-input   [11:0]  pad_bmu_iahbl_mask;              
+input   [15:0]  pad_bmu_iahbl_base;              
+input   [15:0]  pad_bmu_iahbl_mask;              
 input           pad_yy_gate_clk_en_b;            
 input           pad_yy_test_mode;                
 input           tcipif_bmu_dbus_acc_err;         
@@ -1776,8 +1776,8 @@ wire            lsu_bmu_store_error;
 wire    [31:0]  lsu_bmu_wdata;                   
 wire            lsu_bmu_wfd1;                    
 wire            lsu_bmu_write;                   
-wire    [11:0]  pad_bmu_iahbl_base;              
-wire    [11:0]  pad_bmu_iahbl_mask;              
+wire    [15:0]  pad_bmu_iahbl_base;              
+wire    [15:0]  pad_bmu_iahbl_mask;              
 wire            pad_yy_gate_clk_en_b;            
 wire            pad_yy_test_mode;                
 wire            tcipif_bmu_dbus_acc_err;         
@@ -4619,8 +4619,8 @@ input           had_yy_xx_dp_index_mbee;
 input   [31:0]  pad_biu_hrdata;                      
 input           pad_biu_hready;                      
 input           pad_biu_hresp;                       
-input   [11:0]  pad_bmu_iahbl_base;                  
-input   [11:0]  pad_bmu_iahbl_mask;                  
+input   [15:0]  pad_bmu_iahbl_base;                  
+input   [15:0]  pad_bmu_iahbl_mask;                  
 input           pad_cpu_dfs_req;                     
 input           pad_cpu_ext_int_b;                   
 input   [31:0]  pad_iahbl_hrdata;                    
@@ -4932,8 +4932,8 @@ wire            lsu_had_st;
 wire    [31:0]  pad_biu_hrdata;                      
 wire            pad_biu_hready;                      
 wire            pad_biu_hresp;                       
-wire    [11:0]  pad_bmu_iahbl_base;                  
-wire    [11:0]  pad_bmu_iahbl_mask;                  
+wire    [15:0]  pad_bmu_iahbl_base;                  
+wire    [15:0]  pad_bmu_iahbl_mask;                  
 wire            pad_cpu_dfs_req;                     
 wire            pad_cpu_ext_int_b;                   
 wire    [31:0]  pad_iahbl_hrdata;                    
@@ -7614,8 +7614,8 @@ input           clk_en;
 input   [31:0]  pad_biu_hrdata;                      
 input           pad_biu_hready;                      
 input           pad_biu_hresp;                       
-input   [11:0]  pad_bmu_iahbl_base;                  
-input   [11:0]  pad_bmu_iahbl_mask;                  
+input   [15:0]  pad_bmu_iahbl_base;                  
+input   [15:0]  pad_bmu_iahbl_mask;                  
 input   [63:0]  pad_clic_int_cfg;                    
 input   [63:0]  pad_clic_int_vld;                    
 input           pad_cpu_dfs_req;                     
@@ -7799,8 +7799,8 @@ wire            lsu_had_st;
 wire    [31:0]  pad_biu_hrdata;                      
 wire            pad_biu_hready;                      
 wire            pad_biu_hresp;                       
-wire    [11:0]  pad_bmu_iahbl_base;                  
-wire    [11:0]  pad_bmu_iahbl_mask;                  
+wire    [15:0]  pad_bmu_iahbl_base;                  
+wire    [15:0]  pad_bmu_iahbl_mask;                  
 wire    [63:0]  pad_clic_int_cfg;                    
 wire    [63:0]  pad_clic_int_vld;                    
 wire            pad_cpu_dfs_req;                     

diff --git a/soc/core_top.v b/soc/core_top.v
@@ -9,8 +9,8 @@ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLI
 
 */
 module core_top #(
-  parameter IBUS_BASE = 12'h000,
-  parameter IBUS_MASK = 12'he00,
+  parameter IBUS_BASE = 16'h0000,
+  parameter IBUS_MASK = 16'h0000,
   parameter RESET_VECTOR = 32'h0000_0000
 ) (
   apb0_dummy1_intr,
@@ -314,8 +314,8 @@ wire            main_imemdummy0_intr;
 wire    [31:0]  pad_biu_hrdata;        
 wire            pad_biu_hready;        
 wire            pad_biu_hresp;         
-wire    [11:0]  pad_bmu_iahbl_base;    
-wire    [11:0]  pad_bmu_iahbl_mask;    
+wire    [15:0]  pad_bmu_iahbl_base;    
+wire    [15:0]  pad_bmu_iahbl_mask;    
 wire    [63:0]  pad_clic_int_cfg;      
 wire    [63:0]  pad_clic_int_vld;      
 wire            pad_core_clk;          
@@ -482,8 +482,8 @@ end
 assign pll_core_cpuclk             = pll_cpu_clk;
 assign pad_cpu_rst_b               = pad_core_rst_b;
 assign clk_en                      = 1'b1;
-assign pad_bmu_iahbl_base[11:0]    = IBUS_BASE;
-assign pad_bmu_iahbl_mask[11:0]    = IBUS_MASK;
+assign pad_bmu_iahbl_base[15:0]    = IBUS_BASE;
+assign pad_bmu_iahbl_mask[15:0]    = IBUS_MASK;
 assign cpu_wic_ctim_int_vld        = ctim_pad_int_vld;
 assign cpu_pmu_sleep_b	   	   = & sysio_pad_lpmd_b[1:0];
 assign pad_vic_int_cfg[63:0]       = ip_cpu_int_cfg[63:0];

diff --git a/soc/wujian100_open_top.v b/soc/wujian100_open_top.v
@@ -1091,6 +1091,8 @@ pdu_top  x_pdu_top (
   .wdt_wic_intr          (wdt_wic_intr         )
 );
 core_top #(
+  .IBUS_BASE(16'h0000),
+  .IBUS_MASK(16'he000),
   .RESET_VECTOR(32'h0000_0000)
 ) x_cpu_top (
   .apb0_dummy1_intr      (apb0_dummy1_intr     ),
@@ -1184,6 +1186,8 @@ core_top #(
   .mailbox_intr          (mailbox0_intr        )
 );
 core_top #(
+  .IBUS_BASE(16'h2000),
+  .IBUS_MASK(16'hffff),
   .RESET_VECTOR(32'h2000_0000)
 ) x_cpu_top_1 (
   .apb0_dummy1_intr      (apb0_dummy1_intr     ),

diff --git a/wujian100_open.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v b/wujian100_open.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
@@ -1,7 +1,7 @@
 //Copyright 1986-2023 Xilinx, Inc. All Rights Reserved.
 //--------------------------------------------------------------------------------
 //Tool Version: Vivado v.2022.2.2 (win64) Build 3788238 Tue Feb 21 20:00:34 MST 2023
-//Date        : Wed May 24 05:48:24 2023
+//Date        : Wed May 24 07:03:46 2023
 //Host        : ThinPC running 64-bit major release  (build 9200)
 //Command     : generate_target design_1_wrapper.bd
 //Design      : design_1_wrapper

diff --git a/wujian100_open.srcs/sources_1/bd/design_1/design_1.bda b/wujian100_open.srcs/sources_1/bd/design_1/design_1.bda
@@ -23,20 +23,20 @@
   <key id="VT" for="node" attr.name="vert_type" attr.type="string"/>
   <graph id="G" edgedefault="undirected" parse.nodeids="canonical" parse.edgeids="canonical" parse.order="nodesfirst">
     <node id="n0">
+      <data key="VM">design_1</data>
+      <data key="VT">BC</data>
+    </node>
+    <node id="n1">
       <data key="VH">2</data>
       <data key="VM">design_1</data>
       <data key="VT">VR</data>
     </node>
-    <node id="n1">
+    <node id="n2">
       <data key="TU">active</data>
       <data key="VH">2</data>
       <data key="VT">PM</data>
     </node>
-    <node id="n2">
-      <data key="VM">design_1</data>
-      <data key="VT">BC</data>
-    </node>
-    <edge id="e0" source="n2" target="n0"/>
-    <edge id="e1" source="n0" target="n1"/>
+    <edge id="e0" source="n0" target="n1"/>
+    <edge id="e1" source="n1" target="n2"/>
   </graph>
 </graphml>
diff --git a/wujian100_open.xpr b/wujian100_open.xpr
@@ -409,21 +409,21 @@
           <Attr Name="UsedIn" Val="implementation"/>
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
-        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci">
-          <Proxy FileSetName="design_1_clk_wiz_0_0"/>
+        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_vector_logic_1_0/design_1_util_vector_logic_1_0.xci">
+          <Proxy FileSetName="design_1_util_vector_logic_1_0"/>
         </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0.xci">
           <Proxy FileSetName="design_1_processing_system7_0_0"/>
         </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_vector_logic_2_0/design_1_util_vector_logic_2_0.xci">
           <Proxy FileSetName="design_1_util_vector_logic_2_0"/>
         </CompFileExtendedInfo>
+        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_clk_wiz_0_0/design_1_clk_wiz_0_0.xci">
+          <Proxy FileSetName="design_1_clk_wiz_0_0"/>
+        </CompFileExtendedInfo>
         <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_wujian100_open_top_0_0/design_1_wujian100_open_top_0_0.xci">
           <Proxy FileSetName="design_1_wujian100_open_top_0_0"/>
         </CompFileExtendedInfo>
-        <CompFileExtendedInfo CompFileName="design_1.bd" FileRelPathName="ip/design_1_util_vector_logic_1_0/design_1_util_vector_logic_1_0.xci">
-          <Proxy FileSetName="design_1_util_vector_logic_1_0"/>
-        </CompFileExtendedInfo>
       </File>
       <File Path="$PGENDIR/sources_1/bd/design_1/hdl/design_1_wrapper.v">
         <FileInfo>