[LLVM][XTHeadVector] Implement 17.2-17.6 `vmv/vfmv/vslide/vrgather/vc…

…ompress` (llvm#105) * [LLVM][XTHeadVector] Implement 17.2-17.6 `vmv/vfmv/vslide/vrgather/vcompress` * [LLVM][XTHeadVector] Test `vrgather/vcompress` * [LLVM][XTHeadVector] Test `vslide` * [LLVM][XTHeadVector] Test `vslide` for rv32 * [LLVM][XTHeadVector] Fix `vslide1` tests for rv32
revyos · Apr 29, 2024 · 660c32c · 660c32c
1 parent 4638c5b
commit 660c32c
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Showing 13 changed files with 17,114 additions and 34 deletions.
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td b/llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td
@@ -768,6 +768,46 @@ let TargetPrefix = "riscv" in {
     let VLOperand = 4;
   }
 
+  // For destination vector type is the same as first and second source vector.
+  // Input: (vector_in, vector_in, int_vector_in, vl)
+  class XVRGatherVVMasked
+        : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, LLVMMatchType<0>, LLVMVectorOfBitcastsToInt<0>,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty],
+                    [IntrNoMem]>, RISCVVIntrinsic {
+    let VLOperand = 4;
+  }
+
+  // For destination vector type is the same as first source vector (with mask).
+  // Second operand is XLen.
+  // Input: (maskedoff, vector_in, xlen_in, mask, vl)
+  class XVGatherVXMasked
+       : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
+                    LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMMatchType<1>],
+                   [IntrNoMem]>, RISCVVIntrinsic {
+    let VLOperand = 4;
+  }
+
+  // Input: (vector_in, vector_in, scalar_in, vl)
+  class XVSlideUnMasked
+        : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
+                     LLVMMatchType<1>],
+                    [IntrNoMem]>, RISCVVIntrinsic {
+    let VLOperand = 3;
+  }
+
+  // Input: (vector_in, vector_in, vector_in/scalar_in, mask, vl)
+  class XVSlideMasked
+        : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyint_ty,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
+                     LLVMMatchType<1>],
+                    [IntrNoMem]>, RISCVVIntrinsic {
+    let VLOperand = 4;
+  }
+
   multiclass XVBinaryAAX {
     def "int_riscv_" # NAME : RISCVBinaryAAXUnMasked;
     def "int_riscv_" # NAME # "_mask" : XVBinaryAAXMasked;
@@ -832,6 +872,21 @@ let TargetPrefix = "riscv" in {
     def "int_riscv_" # NAME : RISCVUnaryAAUnMaskedRoundingMode;
     def "int_riscv_" # NAME # "_mask" : XVUnaryAAMaskedRoundingMode;
   }
+
+  multiclass XVRGatherVV {
+    def "int_riscv_" # NAME : RISCVRGatherVVUnMasked;
+    def "int_riscv_" # NAME # "_mask" : XVRGatherVVMasked;
+  }
+
+  multiclass XVRGatherVX {
+    def "int_riscv_" # NAME : RISCVGatherVXUnMasked;
+    def "int_riscv_" # NAME # "_mask" : XVGatherVXMasked;
+  }
+
+  multiclass XVSlide {
+    def "int_riscv_" # NAME : XVSlideUnMasked;
+    def "int_riscv_" # NAME # "_mask" : XVSlideMasked;
+  }
 }
 
 let TargetPrefix = "riscv" in {
@@ -1096,4 +1151,41 @@ let TargetPrefix = "riscv" in {
     let VLOperand = 2;
   }
 
+  // 17.2. Integer Scalar Move Operations
+  def int_riscv_th_vmv_x_s : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+                                                   [llvm_anyint_ty],
+                                                   [IntrNoMem]>, RISCVVIntrinsic;
+  def int_riscv_th_vmv_s_x : DefaultAttrsIntrinsic<[llvm_anyint_ty],
+                                                   [LLVMMatchType<0>,
+                                                    LLVMVectorElementType<0>,
+                                                    llvm_anyint_ty],
+                                                   [IntrNoMem]>, RISCVVIntrinsic {
+    let VLOperand = 2;
+  }
+
+  // 17.3. Floating-Point Scalar Move Operations
+  def int_riscv_th_vfmv_f_s : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
+                                                    [llvm_anyfloat_ty],
+                                                    [IntrNoMem]>, RISCVVIntrinsic;
+  def int_riscv_th_vfmv_s_f : DefaultAttrsIntrinsic<[llvm_anyfloat_ty],
+                                                    [LLVMMatchType<0>,
+                                                     LLVMVectorElementType<0>,
+                                                     llvm_anyint_ty],
+                                                    [IntrNoMem]>, RISCVVIntrinsic {
+    let VLOperand = 2;
+  }
+
+  // 17.4. Vector Slide Operations
+  defm th_vslideup     : XVSlide;
+  defm th_vslidedown   : XVSlide;
+  defm th_vslide1up    : XVBinaryAAX;
+  defm th_vslide1down  : XVBinaryAAX;
+
+  // 17.5. Vector Register Gather Operations
+  defm th_vrgather_vv : XVRGatherVV;
+  defm th_vrgather_vx : XVRGatherVX;
+
+  // 17.6. Vector Compress Operations
+  def int_riscv_th_vcompress : RISCVCompress;
+
 } // TargetPrefix = "riscv"