[LLVM][XTHeadVector] Implement intrinsics for vnclipu/vnclip. (llvm#86)

* [LLVM][XTHeadVector] Define intrinsic functions.

* [LLVM][XTHeadVector] Define pseudos and pats.

* [LLVM][XTHeadVector] Add test cases.

* [NFC][XTHeadVector] Update Readme.

README.md

@@ -56,6 +56,7 @@ Any feature not listed below but present in the specification should be consider
     - (Done) `13.1. Vector Single-Width Saturating Add and Subtract`
     - (Done) `13.2. Vector Single-Width Averaging Add and Subtract`
     - (Done) `13.3. Vector Single-Width Fractional Multiply with Rounding and Saturation`
+    - (Done) `13.6. Vector Narrowing Fixed-Point Clip Instructions`
 - (WIP) Clang intrinsics related to the `XTHeadVector` extension:
   - (WIP) `6. Configuration-Setting and Utility`
     - (Done) `6.1. Set vl and vtype`

llvm/include/llvm/IR/IntrinsicsRISCVXTHeadV.td

@@ -680,6 +680,20 @@ let TargetPrefix = "riscv" in {
     let VLOperand = 4;
   }
 
+  // For Saturating binary operations with mask but no policy.
+  // The destination vector type is NOT the same as first source vector (with mask).
+  // The second source operand matches the destination type or is an XLen scalar.
+  // Input: (maskedoff, vector_in, vector_in/scalar_in, mask, vxrm, vl)
+  class XVSaturatingBinaryABShiftMaskedRoundingMode
+        : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+                    [LLVMMatchType<0>, llvm_anyvector_ty, llvm_any_ty,
+                     LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, llvm_anyint_ty,
+                     LLVMMatchType<3>],
+                    [ImmArg<ArgIndex<4>>, IntrNoMem, IntrHasSideEffects]>,
+                    RISCVVIntrinsic {
+    let VLOperand = 5;
+  }
+
   multiclass XVBinaryAAX {
     def "int_riscv_" # NAME : RISCVBinaryAAXUnMasked;
     def "int_riscv_" # NAME # "_mask" : XVBinaryAAXMasked;
@@ -719,6 +733,11 @@ let TargetPrefix = "riscv" in {
     def "int_riscv_" # NAME : RISCVSaturatingBinaryAAXUnMasked;
     def "int_riscv_" # NAME # "_mask" : XVSaturatingBinaryAAXMasked;
   }
+
+  multiclass XVSaturatingBinaryABShiftRoundingMode {
+    def "int_riscv_" # NAME : RISCVSaturatingBinaryABShiftUnMaskedRoundingMode;
+    def "int_riscv_" # NAME # "_mask" : XVSaturatingBinaryABShiftMaskedRoundingMode;
+  }
 }
 
 let TargetPrefix = "riscv" in {
@@ -841,4 +860,8 @@ let TargetPrefix = "riscv" in {
   // 13.3.  Vector Single-Width Fractional Multiply with Rounding and Saturation Instructions
   defm th_vsmul : XVBinaryAAXRoundingMode;
 
+  // 13.6. Vector Narrowing Fixed-Point Clip Instructions
+  defm th_vnclipu : XVSaturatingBinaryABShiftRoundingMode;
+  defm th_vnclip : XVSaturatingBinaryABShiftRoundingMode;
+
 } // TargetPrefix = "riscv"

llvm/lib/Target/RISCV/RISCVInstrInfoXTHeadVPseudos.td

@@ -1797,6 +1797,24 @@ multiclass XVPseudoTernaryW_VX<LMULInfo m> {
                                      constraint>;
 }
 
+multiclass XVPseudoBinaryV_WV_RM<LMULInfo m> {
+  defm _WV : XVPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, m.vrclass, m,
+                                        !if(!ge(m.octuple, 8),
+                                        "@earlyclobber $rd", "")>;
+}
+
+multiclass XVPseudoBinaryV_WX_RM<LMULInfo m> {
+  defm _WX : XVPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, GPR, m,
+                                        !if(!ge(m.octuple, 8),
+                                        "@earlyclobber $rd", "")>;
+}
+
+multiclass XVPseudoBinaryV_WI_RM<LMULInfo m> {
+  defm _WI : XVPseudoBinaryRoundingMode<m.vrclass, m.wvrclass, uimm5, m,
+                                        !if(!ge(m.octuple, 8),
+                                        "@earlyclobber $rd", "")>;
+}
+
 multiclass XVPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxListXTHeadV in {
     defvar mx = m.MX;
@@ -2183,6 +2201,24 @@ multiclass XVPseudoVSMUL_VV_VX_RM {
   }
 }
 
+multiclass XVPseudoVNCLP_WV_WX_WI_RM {
+  foreach m = MxListWXTHeadV in {
+    defvar mx = m.MX;
+    defvar WriteVNClipV_MX = !cast<SchedWrite>("WriteVNClipV_" # mx);
+    defvar WriteVNClipX_MX = !cast<SchedWrite>("WriteVNClipX_" # mx);
+    defvar WriteVNClipI_MX = !cast<SchedWrite>("WriteVNClipI_" # mx);
+    defvar ReadVNClipV_MX = !cast<SchedRead>("ReadVNClipV_" # mx);
+    defvar ReadVNClipX_MX = !cast<SchedRead>("ReadVNClipX_" # mx);
+
+    defm "" : XVPseudoBinaryV_WV_RM<m>,
+              Sched<[WriteVNClipV_MX, ReadVNClipV_MX, ReadVNClipV_MX, ReadVMask]>;
+    defm "" : XVPseudoBinaryV_WX_RM<m>,
+              Sched<[WriteVNClipX_MX, ReadVNClipV_MX, ReadVNClipX_MX, ReadVMask]>;
+    defm "" : XVPseudoBinaryV_WI_RM<m>,
+              Sched<[WriteVNClipI_MX, ReadVNClipV_MX, ReadVMask]>;
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Helpers to define the intrinsic patterns for the XTHeadVector extension.
 //===----------------------------------------------------------------------===//
@@ -2727,6 +2763,52 @@ multiclass XVPseudoVSALU_VV_VX {
   }
 }
 
+multiclass XVPatBinaryV_WV_RM<string intrinsic, string instruction,
+                              list<VTypeInfoToWide> vtilist> {
+  foreach VtiToWti = vtilist in {
+    defvar Vti = VtiToWti.Vti;
+    defvar Wti = VtiToWti.Wti;
+    let Predicates = !listconcat(GetXVTypePredicates<Vti>.Predicates,
+                                 GetXVTypePredicates<Wti>.Predicates) in
+    defm : XVPatBinaryRoundingMode<intrinsic,
+                                   instruction # "_WV_" # Vti.LMul.MX,
+                                   Vti.Vector, Wti.Vector, Vti.Vector, Vti.Mask,
+                                   Vti.Log2SEW, Vti.RegClass,
+                                   Wti.RegClass, Vti.RegClass>;
+  }
+}
+
+multiclass XVPatBinaryV_WX_RM<string intrinsic, string instruction,
+                              list<VTypeInfoToWide> vtilist> {
+  foreach VtiToWti = vtilist in {
+    defvar Vti = VtiToWti.Vti;
+    defvar Wti = VtiToWti.Wti;
+    defvar kind = "W"#Vti.ScalarSuffix;
+    let Predicates = !listconcat(GetXVTypePredicates<Vti>.Predicates,
+                                 GetXVTypePredicates<Wti>.Predicates) in
+    defm : XVPatBinaryRoundingMode<intrinsic,
+                                   instruction#"_"#kind#"_"#Vti.LMul.MX,
+                                   Vti.Vector, Wti.Vector, Vti.Scalar, Vti.Mask,
+                                   Vti.Log2SEW, Vti.RegClass,
+                                   Wti.RegClass, Vti.ScalarRegClass>;
+  }
+}
+
+multiclass XVPatBinaryV_WI_RM<string intrinsic, string instruction,
+                              list<VTypeInfoToWide> vtilist> {
+  foreach VtiToWti = vtilist in {
+    defvar Vti = VtiToWti.Vti;
+    defvar Wti = VtiToWti.Wti;
+    let Predicates = !listconcat(GetXVTypePredicates<Vti>.Predicates,
+                                 GetXVTypePredicates<Wti>.Predicates) in
+    defm : XVPatBinaryRoundingMode<intrinsic,
+                                   instruction # "_WI_" # Vti.LMul.MX,
+                                   Vti.Vector, Wti.Vector, XLenVT, Vti.Mask,
+                                   Vti.Log2SEW, Vti.RegClass,
+                                   Wti.RegClass, uimm5>;
+  }
+}
+
 multiclass XVPatBinaryV_VV_VX_VI<string intrinsic, string instruction,
                                  list<VTypeInfo> vtilist, Operand ImmType = simm5>
     : XVPatBinaryV_VV<intrinsic, instruction, vtilist>,
@@ -2808,6 +2890,12 @@ multiclass XVPatTernaryW_VV_VX<string intrinsic, string instruction,
     : XVPatTernaryW_VV<intrinsic, instruction, vtilist>,
       XVPatTernaryW_VX<intrinsic, instruction, vtilist>;
 
+multiclass XVPatBinaryV_WV_WX_WI_RM<string intrinsic, string instruction,
+                                    list<VTypeInfoToWide> vtilist>
+    : XVPatBinaryV_WV_RM<intrinsic, instruction, vtilist>,
+      XVPatBinaryV_WX_RM<intrinsic, instruction, vtilist>,
+      XVPatBinaryV_WI_RM<intrinsic, instruction, vtilist>;
+
 //===----------------------------------------------------------------------===//
 // 12.1. Vector Single-Width Saturating Add and Subtract
 //===----------------------------------------------------------------------===//
@@ -3286,4 +3374,19 @@ let Predicates = [HasVendorXTHeadV] in {
   defm : XVPatBinaryV_VV_VX_RM<"int_riscv_th_vsmul", "PseudoTH_VSMUL", AllIntegerXVectors>;
 } // Predicates = [HasVendorXTHeadV]
 
+//===----------------------------------------------------------------------===//
+// 13.6. Vector Narrowing Fixed-Point Clip Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasVendorXTHeadV], Defs = [VXSAT], hasSideEffects = 1 in {
+  defm PseudoTH_VNCLIP  : XVPseudoVNCLP_WV_WX_WI_RM;
+  defm PseudoTH_VNCLIPU : XVPseudoVNCLP_WV_WX_WI_RM;
+} // Predicates = [HasVendorXTHeadV]
+
+let Predicates = [HasVendorXTHeadV] in {
+  defm : XVPatBinaryV_WV_WX_WI_RM<"int_riscv_th_vnclipu", "PseudoTH_VNCLIPU",
+                                  AllWidenableIntXVectors>;
+  defm : XVPatBinaryV_WV_WX_WI_RM<"int_riscv_th_vnclip", "PseudoTH_VNCLIP",
+                                   AllWidenableIntXVectors>;
+} // Predicates = [HasVendorXTHeadV]
+
 include "RISCVInstrInfoXTHeadVVLPatterns.td"