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Merge pull request #150 from riscv-software-src/149-update-mc-1-crd-s…
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…ince-risc-v-summit-is-tomorrow

Cleanup of CRD before Summit
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dhower-qc authored Oct 21, 2024
2 parents 7e0ba67 + 770ed24 commit 2ae213d
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57 changes: 1 addition & 56 deletions arch/crd/MC-1.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -77,59 +77,4 @@ MC-1:
const: little
XLEN:
schema:
const: 32

requirement_groups:
- name: MC-Unpriv
description: |
The MC-Unpriv defines unprivileged ISA requirements.
Note that unprivileged ISA features are those that are usable in all privilege modes;
they aren't only usable in U-mode (User-mode).
It is unfortunate that both “Unprivileged” and “User” start with the letter “U” but they
aren't the same thing.
requirements:
- name: REQ-UINST-001
description: Should use little-endian byte order

- name: REQ-UCSR-001-a
description: Should raise an Illegal Instruction exception when writing to the `cycle` CSR

- name: REQ-UCSR-001-b
description: Should return the XLEN least-significant bits of the `mcycle` CSR when reading the `cycle` CSR

- name: REQ-UCSR-002-a
description: Should raise an Illegal Instruction exception when writing to the `time` CSR

- name: REQ-UCSR-002-b
description: Should return the XLEN least-significant bits of the `mtime` CSR when reading the `time` CSR
when:
param:
TIME_CSR_IMPLEMENTED: true

- name: REQ-UCSR-002-c
description: Should raise an Illegal Instruction exception when reading the `time` CSR
when:
param:
TIME_CSR_IMPLEMENTED: false

- name: MC-Unpriv-32
when:
xlen: 32
description: |
The MC-Unpriv-32 defines unprivileged ISA requirements specific to 32-bit processors.
requirements:
- name: REQ-M32CSR-001-a
description: Should raise an illegal instruction trap when writing the 'cycleh' CSR
- name: REQ-M32CSR-001-b
description: Should return the most-significant 32-bits of the `mcycle` CSR when reading `cycleh`
- name: REQ-M32CSR-002
description: Should return the most-significant 32-bits of the `minstret` CSR when reading `instreth`

- name: MC-Priv
description: |
The MC-Priv defines Privileged ISA requirements.
requirements:
- name: REQ-PRIV-HARTID
description: |
One hart in system has to have a HARTID of 0. Reading `mhartid` on other CSRs provides some value.
const: 32
2 changes: 1 addition & 1 deletion arch/csr/mip.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ mip:
address: 0x344
priv_mode: M
description: Machine Interrupt Pending bits
length: 64
length: MXLEN
definedBy: Sm
fields:
SSIP:
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7 changes: 4 additions & 3 deletions arch/csr/mscratch.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,13 @@ mscratch:
long_name: Machine Scratch Register
address: 0x340
priv_mode: M
length: 64
length: MXLEN
description: Scratch register for software use. Bits are not interpreted by hardware.
definedBy: U # actually, defined by RV64, but must implement U-mode for this CSR to exist
definedBy: Sm
fields:
SCRATCH:
location: 63-0
location_rv32: 31-0
location_rv64: 63-0
description: Scratch value
type: RW
reset_value: 0
5 changes: 3 additions & 2 deletions arch/csr/mtval.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -5,11 +5,12 @@ mtval:
address: 0x343
description: Holds trap-specific information
priv_mode: M
length: 64
length: MXLEN
definedBy: Sm
fields:
VALUE:
location: 63-0
location_rv32: 31-0
location_rv64: 63-0
description: |
Written with trap-specific information when a trap is taken into M-mode.
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12 changes: 6 additions & 6 deletions arch/ext/Sm.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -231,7 +231,7 @@ Sm:
description: |
Does the implementation perform non-atomic misaligned loads and stores to main memory
(does *not* affect misaligned support to device memory)?
If not, the implementation throws a misaligned exception.
If not, the implementation always throws a misaligned exception.
schema:
type: boolean
MISALIGNED_LDST_EXCEPTION_PRIORITY:
Expand All @@ -247,21 +247,21 @@ Sm:
! high ! Misaligned load/store/AMO exceptions are always higher priority than load/store/AMO page-fault and access-fault exceptions.
!===
MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be "high" when MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE
MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be "high" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE
is non-zero, since the atomicity of an access cannot be determined in that case until after
address translation.
schema:
type: string
enum: ["low", "high"]
extra_validation: |
assert (MISALIGNED_LDST_EXCEPTION_PRIORITY == "low") if MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE.positive?
MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE:
assert (MISALIGNED_LDST_EXCEPTION_PRIORITY == "low") if MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE.positive?
MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE:
description: |
The maximum granule size, in bytes, that the hart can atomically perform a
misaligned load/store/AMO without raising a Misaligned exception. When MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE is 0, the hart
misaligned load/store/AMO without raising a Misaligned exception. When MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is 0, the hart
cannot atomically perform a misaligned load/store/AMO. When a power of two, the hart can
atomically load/store/AMO a misaligned access that is fully contained in a
MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE-aligned region.
MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE-aligned region.
[NOTE]
Even if the hart is capable of performing a misaligned load/store/AMO atomically,
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6 changes: 3 additions & 3 deletions arch/isa/globals.isa
Original file line number Diff line number Diff line change
Expand Up @@ -2367,7 +2367,7 @@ function misaligned_is_atomic? {
body {
# if the hart doesn't support Misligned Atomicity Granules,
# then this misligned access is not atomic
return false if MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE == 0;
return false if MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE == 0;

if (pma_applies?(PmaAttribute::MAG16, physical_address, N) &&
in_naturally_aligned_region?<128>(physical_address, N)) {
Expand Down Expand Up @@ -2434,7 +2434,7 @@ function read_memory {
# access isn't naturally aligned, but it still might be atomic if this hart supports
# Misliagned Atomicity Granules. We won't know that, though, until after translation since PMAs
# apply to physical addresses
if (MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE > 0) {
if (MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE > 0) {
# sanity check that the implementation isn't expecting a Misaligned exception
# before an access/page fault exception (that would be an invalid config)
assert(MISALIGNED_LDST_EXCEPTION_PRIORITY == "low", "Invalid config: can't mix low-priority misaligned exceptions with large atomicity granule");
Expand Down Expand Up @@ -2758,7 +2758,7 @@ function write_memory {
# access isn't naturally aligned, but it still might be atomic if this hart supports
# Misliagned Atomicity Granules. We won't know that, though, until after translation since PMAs
# apply to physical addresses
if (MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE > 0) {
if (MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE > 0) {
# sanity check that the implementation isn't expecting a Misaligned exception
# before an access/page fault exception (that would be an invalid config)
assert(MISALIGNED_LDST_EXCEPTION_PRIORITY == "low", "Invalid config: can't mix low-priority misaligned exceptions with large atomicity granule");
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2 changes: 2 additions & 0 deletions backends/crd_doc/templates/crd.adoc.erb
Original file line number Diff line number Diff line change
Expand Up @@ -209,6 +209,7 @@ None
<% end # do -%>
|===
<% unless crd.requirement_groups.empty? -%>
== Additional Requirements
This section contains requirements in addition to those already specified related to extensions and parameters.
Expand Down Expand Up @@ -239,6 +240,7 @@ Requirement <%= req.name %> only apply when <%= req.when_pretty %>.
|===
<% end -%>
<% end # unless requirement_groups.empty? -%>
[appendix]
== Extension Details
Expand Down
2 changes: 1 addition & 1 deletion cfgs/generic_rv64/params.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ params:

MISALIGNED_LDST_EXCEPTION_PRIORITY: high

MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE: 0
MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: 0

MISALIGNED_SPLIT_STRATEGY: by_byte

Expand Down
2 changes: 1 addition & 1 deletion lib/DB_MODEL.README.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,7 @@ A YAML file with values for parameters defined by the implemented extensions. Pa
params:
MISALIGNED_LDST: true
MISALIGNED_LDST_EXCEPTION_PRIORITY: high
MAX_MISALIGNED_ATOMICITY_GRANULE_SIZE: 0
MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE: 0
MISALIGNED_SPLIT_STRATEGY: by_byte
# ...
----
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2 changes: 1 addition & 1 deletion lib/arch_obj_models/crd.rb
Original file line number Diff line number Diff line change
Expand Up @@ -473,7 +473,7 @@ def requirement_groups
return @requirement_groups unless @requirement_groups.nil?

@requirement_groups = []
@data["requirement_groups"].each do |req_group|
@data["requirement_groups"]&.each do |req_group|
@requirement_groups << RequirementGroup.new(req_group, @arch_def)
end
@requirement_groups
Expand Down
2 changes: 1 addition & 1 deletion schemas/csr_schema.json
Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@
},
"type()": {
"type": "string",
"description": "Function that returns a configuratin-depenent type. The return value should be a CsrFieldType enum, and must be compile-time-known."
"description": "Function that returns a configuration-depenent type. The return value should be a CsrFieldType enum, and must be compile-time-known."
},
"alias": {
"oneOf": [
Expand Down

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