Add HaDes-V

Signed-off-by: Rafael Sene <rafael@riscv.org>

README.md

@@ -112,6 +112,7 @@ Tools to enhance understanding or visualize the RISC-V ISA.
 | **emulsiV** | Guillaume Savaton | Visual simulator for a minimal 32-bit RISC processor. | [Website](https://eseo-tech.github.io/emulsiV/) | 2023-20-12 |
 | **Go RISC-V Emulator** | Lucas Teske | A golang implementation of RV32I+M that can run doom | [GitHub](https://github.com/racerxdl/riscv-emulator) | 2024-18-10 |
 | **GodBolt** | Matt Godbolt | Online Compiler Explorer that supports GCC/LLVM for RV64 | [Website](https://godbolt.org/) | 2024-18-10 |
+| **HaDes-V** | Tobias Scheipel | [The Instruction Guide](https://repository.tugraz.at/oer/nytm4-grv34) and this source code template for the [Microcontroller Design, Lab](https://online.tugraz.at/tug_online/ee/ui/ca2/app/desktop/#/slc.tm.cp/student/courses/525082?$scrollTo=toc_overview) is an Open Educational Resource (OER) developed by [Tobias Scheipel](https://www.scheipel.com/), David Beikircher, and Florian Riedl, Embedded Architectures & Systems Group at Graz University of Technology. It is designed for teaching and learning microcontroller design and hardware description languages, using the HaDes-V architecture, a RISC-V-based processor. | [GitHub](https://github.com/tscheipel/HaDes-V/) | 2024-18-12 |
 | **Online RISC-V Assembler** | Lucas Teske | Online RISC-V Assembler using gnu-assembler in webassembly | [Website](https://riscvasm.lucasteske.dev/) , [Github](https://github.com/racerxdl/riscv-online-asm) | 2024-18-10 |
 | **Piscado** | GustavonMartis | RISC-V Simulator written in python during twitch live coding | [Github](https://github.com/gustavonmartins/piscado) | 2024-18-10 |
 | **QtRvSim** | CTU Prague | RISC-V simulator with cache and pipeline visualization. | [GitHub](https://github.com/cvut/qtrvsim/) | 2023-20-12 |