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spec: scalar: es wording and oeprating mode fixes
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	modified:   riscv-crypto-scalar-entropy-source.adoc
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ben-marshall committed Sep 1, 2021
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18 changes: 10 additions & 8 deletions doc/scalar/riscv-crypto-scalar-entropy-source.adoc
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Expand Up @@ -16,9 +16,9 @@ See <<crypto_scalar_appx_es>> for a non-normative description of a
certification and self-certification procedures, design rationale, and more detailed suggestions on how the entropy source output can be used.

[[crypto_scalar_seed_csr]]
=== the seed CSR
=== The seed CSR

The `seed` CSR is located at address `0x015`.
`seed` is a user mode CSR located at address `0x015`.
The 32-bit contents of `seed` are as follows:

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Expand All @@ -38,8 +38,10 @@ The 32-bit contents of `seed` are as follows:
The `seed` CSR must be accessed with a read-write instruction. A read-only
instruction such as `CSRRS/CSRRC` with `rs1=x0` or `CSRRSI/CSRRCI` with
`uimm=0` will raise an illegal instruction exception.
The write value (in `rs1` or `uimm`) should be ignored by implementations.
Its purpose is to merely signal polling and flushing.
The write value (in `rs1` or `uimm`) must be ignored by implementations.
Its purpose is to signal polling and flushing, and avoid introducing

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@mjosaarinen

mjosaarinen Sep 1, 2021

Collaborator

This is a bit confusing. We want those side-effects (like wipe-on-read), right?

side effects (i.e. wipe-on-read, described below) due to a CSR read into the
architecture.

The instruction `csrrw rd, seed, x0` can be used for fetching seed status
and entropy values. It is available on both RV32 and RV64 base architectures
Expand Down Expand Up @@ -262,22 +264,22 @@ other non-`M` modes will raise an Illegal Instruction Exception.
CSR read-write instruction. Attempted read without a write raises an
Illegal Instruction Exception regardless of mode access control bits).

| `S/HS`
| `S/HS/VS`
| `0`
| `*`
| Any `seed` CSR access raises an Illegal Instruction Exception.

| `S/HS`
| `S/HS/VS`
| `1`
| `*`
| The `seed` CSR is accessible as normal. No exception is raised for read-write.

| `U/HU`
| `U/VU`
| `*`
| `0`
| Any `seed` CSR access raises an Illegal Instruction Exception.

| `U/HU`
| `U/VU`
| `*`
| `1`
| The `seed` CSR is accessible as normal. No exception is raised for read-write.
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