1.0.0-rc2

Sdext.adoc

@@ -194,12 +194,6 @@ specified by {dcsr-prv} and {dcsr-v}.
 . If the new privilege mode is less privileged than M-mode, `MPRV` in `mstatus` is cleared.
 . The hart is no longer in debug mode.
 
-=== XLEN
-
-While in Debug Mode, XLEN is DXLEN. It is up to the debugger to
-determine the XLEN during normal program execution (by looking at `misa`) and
-to clearly communicate this to the user.
-
 [[debreg]]
 === Core Debug Registers
 

Sdtrig.adoc

@@ -118,7 +118,7 @@ Instruction address misaligned +
 Environment call +
 Environment break +
 Load/Store/AMO address breakpoint
-.>| mcontrol/mcontrol6 load/store address/data before
+.>| mcontrol/mcontrol6 load/store address before, store data before
 || 4, 6 | Optionally: Load/Store/AMO address misaligned |
 || 13, 15, 21, 23, 5, 7 | During address translation for an explicit
 memory access: First encountered page fault, guest-page fault, or access
@@ -370,4 +370,4 @@ trigger firing at a different time than is expected.
 Attempts to access an unimplemented Trigger Module Register raise an illegal
 instruction exception.
 
-include::build/hwbp_registers.adoc[]
+include::build/hwbp_registers.adoc[]

debug_module.adoc

@@ -100,7 +100,10 @@ The Debug Module's own state and registers should only be reset at
 power-up and while {dmcontrol-dmactive} in {dm-dmcontrol} is 0. If there is another mechanism to reset the DM, this mechanism must also reset all the harts accessible to the DM.
 
 Due to clock and power domain crossing issues, it might not be possible
-to perform arbitrary DMI accesses across hardware platform reset. While {dmcontrol-ndmreset}  or any external reset is asserted, the only supported DM operations are reading and writing {dm-dmcontrol}. The behavior of other accesses is undefined.
+to perform arbitrary DMI accesses across hardware platform reset. While
+{dmcontrol-ndmreset}  or any external reset is asserted, the only supported DM
+operations are reading/writing {dm-dmcontrol} and reading
+{dmstatus-ndmresetpending}. The behavior of other accesses is undefined.
 
 When harts have been reset, they must set a sticky `havereset` state
 bit. The conceptual `havereset` state bits can be read for selected

introduction.adoc

@@ -253,6 +253,16 @@ https://github.com/riscv/riscv-debug-spec/pull/731[#731]
 https://github.com/riscv/riscv-debug-spec/pull/723[#723].
 https://github.com/riscv/riscv-debug-spec/pull/880[#880]
 
+===== Incompatible Changes Between 1.0.0-rc1 and 1.0.0-rc2
+
+Backwards-incompatible changes between 1.0.0-rc1 and 1.0.0-rc2.
+
+. https://github.com/riscv/riscv-debug-spec/pull/981[#981] made
+{csr-scontext}.{scontext-data}, {csr-mcontext}.{mcontext-hcontext},
+{textra64-sbytemask}, and {csr-textra64}.`svalue` narrower. This avoids confusion
+about the contents of {csr-scontext} and {csr-mcontext} when XLEN is reduced and
+increased again.
+
 === About This Document
 
 ==== Structure

riscv-debug-header.adoc

@@ -4,7 +4,7 @@
 :company: RISC-V.org
 :authors: Tim Newsome, Paul Donahue (Ventana Micro Systems)
 :revdate: Revised 2024-01-25
-:revnumber: 1.0.0-rc1
+:revnumber: 1.0.0-rc2
 :revremark: Frozen
 :url-riscv: http://riscv.org
 :doctype: book

xml/hwbp_registers.xml

@@ -13,8 +13,8 @@ same project unless stated otherwise.
     and Debug Mode to prevent untrusted user code from causing entry into Debug
     Mode without the OS's permission.
 
-    In this section XLEN means MXLEN when in M-mode, and DXLEN when in Debug
-    Mode. On systems where those values of XLEN can differ, this is handled
+    In this section XLEN refers to the effective XLEN in the current execution
+    mode. On systems where XLEN values can differ between modes, this is handled
     as follows.
     Fields retain their values regardless of XLEN, which only affects where
     in the register these fields appear (e.g. {tdata1-type}). Some fields
@@ -256,14 +256,15 @@ same project unless stated otherwise.
         `hstateenzero[57]` in the Smstateen extension.  Enabling {csr-scontext}
         can be a security risk in a virtualized system with a hypervisor that
         does not swap {csr-scontext}.
-        <field name="data" bits="XLEN-1:0" access="WARL" reset="0">
+        <field name="0" bits="XLEN-1:32" access="R" reset="0" />
+        <field name="data" bits="31:0" access="WARL" reset="0">
             Supervisor mode software can write a context number to this
             register, which can be used to set triggers that only fire in that
             specific context.
 
             An implementation may tie any number of high bits in this field to
-            0. It's recommended to implement no more than 16 bits on RV32, and
-            34 on RV64.
+            0. It's recommended to implement 16 bits on RV32 and 32 bits on
+            RV64.
         </field>
     </register>
 
@@ -279,17 +280,18 @@ same project unless stated otherwise.
             hypervisor directly.
         ====
 
-        <field name="hcontext" bits="XLEN-1:0" access="WARL" reset="0">
+        <field name="0" bits="XLEN-1:14" access="R" reset="0" />
+        <field name="hcontext" bits="13:0" access="WARL" reset="0">
             M-Mode or HS-Mode (using {csr-hcontext}) software can write a context
             number to this register, which can be used to set triggers that only
             fire in that specific context.
 
             An implementation may tie any number of upper bits in this field to
             0. If the H extension is not implemented, it's recommended to implement
-            no more than 6 bits on RV32 and 13 on RV64 (as visible through the
+            6 bits on RV32 and 13 bits on RV64 (as visible through the
             {csr-mcontext} register).  If the H extension is implemented,
-            it's recommended to implement no more than 7 bits on RV32
-            and 14 on RV64.
+            it's recommended to implement 7 bits on RV32
+            and 14 bits on RV64.
         </field>
     </register>
 
@@ -1401,6 +1403,10 @@ same project unless stated otherwise.
         This register is accessible as {csr-tdata3} when {tdata1-type} is 2, 3, 4,
         5, or 6 and XLEN=32.
 
+        If DXLEN &gt;= 64, then this register provides access to the low bits of
+        each field defined in {csr-textra64}. Writes to this register will clear
+        the high bits of the corresponding fields in {csr-textra64}.
+
         All functionality in this register is optional.  Any number of upper
         bits of {textra32-mhvalue} and {textra32-svalue} may be tied to 0.
         {textra32-mhselect} and {textra32-sselect} may only support 0 (ignore).
@@ -1494,8 +1500,9 @@ same project unless stated otherwise.
         The reset values listed here apply to every underlying trigger.
 
         This register is accessible as {csr-tdata3} when {tdata1-type} is 2, 3, 4,
-        5, or 6 and XLEN=64. The fields are defined
-        above, in {csr-textra32}.
+        5, or 6 and XLEN=64. The function of the fields are defined
+        above, in {csr-textra32}. This register retains its value when XLEN
+        changes. When XLEN=32 some of the bits can be accessed through {csr-textra32}.
 
         Byte-granular comparison of {csr-scontext} to {textra64-svalue} in
         {csr-textra64} allows {csr-scontext} to be defined to include
@@ -1511,17 +1518,17 @@ same project unless stated otherwise.
         <field name="mhselect" bits="50:48" access="WARL" reset="0">
         </field>
 
-        <field name="0" bits="47:41" access="R" reset="0" />
+        <field name="0" bits="47:40" access="R" reset="0" />
 
-        <field name="sbytemask" bits="40:36" access="WARL" reset="0">
+        <field name="sbytemask" bits="39:36" access="WARL" reset="0">
             When the least significant bit of this field is 1, it causes bits 7:0
             in the comparison to be ignored, when {textra64-sselect}=1.
             Likewise, the second bit controls the comparison of bits 15:8,
             third bit controls the comparison of bits 23:16,
-            fourth bit controls the comparison of bits 31:24, and
-            fifth bit controls the comparison of bits 33:32.
+            and fourth bit controls the comparison of bits 31:24.
         </field>
-        <field name="svalue" bits="35:2" access="WARL" reset="0">
+        <field name="0" bits="35:34" access="R" reset="0" />
+        <field name="svalue" bits="33:2" access="WARL" reset="0">
         </field>
         <field name="sselect" bits="1:0" access="WARL" reset="0">
         </field>