Improve Sscofpmf section headers

src/sscofpmf.adoc

@@ -26,9 +26,7 @@ extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering).
 Note that the new count overflow interrupt will be treated as a standard local
 interrupt that is assigned to bit 13 in the mip/mie/sip/sie registers.
 
-=== Machine Level Additions
-
-==== Hardware Performance Monitor
+=== Count Overflow Control
 
 The following bits are added to `mhpmevent`:
 
@@ -105,9 +103,7 @@ maintaining a bit mask reflecting which counters are active and due to
 eventually overflow.
 ====
 
-=== Supervisor Level Additions
-
-==== Supervisor Count Overflow (scountovf)
+=== Supervisor Count Overflow (scountovf) CSR
 
 This extension adds the `scountovf` CSR,
 a 32-bit read-only register that contains shadow copies of