wavedrom adoc to edn second batch (#1586)

* Changing .adoc to .edu for wavedrom files * more adoc to edn * Update src/rv32.adoc Signed-off-by: Kersten Richter <kersten@riscv.org> --------- Signed-off-by: Kersten Richter <kersten@riscv.org>
riscv · Aug 7, 2024 · f20f561 · f20f561
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diff --git a/src/a-st-ext.adoc b/src/a-st-ext.adoc
@@ -54,7 +54,7 @@ same address domain.
 [[sec:lrsc]]
 === "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions
 
-include::images/wavedrom/load-reserve-st-conditional.adoc[]
+include::images/wavedrom/load-reserve-st-conditional.edn[]
 
 Complex atomic memory operations on a single memory word or doubleword
 are performed with the load-reserved (LR) and store-conditional (SC)

diff --git a/src/d-st-ext.adoc b/src/d-st-ext.adoc
@@ -103,7 +103,7 @@ value from the floating-point registers to memory.
 The double-precision value may be a NaN-boxed single-precision value.
 ====
 
-include::images/wavedrom/double-ls.adoc[]
+include::images/wavedrom/double-ls.edn[]
 [[double-ls]]
 //.Double-precision load and store
 
@@ -119,7 +119,7 @@ The double-precision floating-point computational instructions are
 defined analogously to their single-precision counterparts, but operate
 on double-precision operands and produce double-precision results.
 
-include::images/wavedrom/double-fl-compute.adoc[]
+include::images/wavedrom/double-fl-compute.edn[]
 [[fl-compute]]
 //.Double-precision float computational
 
@@ -143,7 +143,7 @@ All floating-point to integer and integer to floating-point conversion
 instructions round according to the _rm_ field. Note FCVT.D.W[U] always
 produces an exact result and is unaffected by rounding mode.
 
-include::images/wavedrom/double-fl-convert-mv.adoc[]
+include::images/wavedrom/double-fl-convert-mv.edn[]
 [[fl-convert-mv]]
 //.Double-precision float convert and move
 
@@ -157,7 +157,7 @@ never round.
 (((double-precision, to single-precision)))
 (((single-precision, to double-precision )))
 
-include::images/wavedrom/fcvt-sd-ds.adoc[]
+include::images/wavedrom/fcvt-sd-ds.edn[]
 [[fcvt-sd-ds]]
 //.Double-precision FCVT.S.D and FCVT.D.S
 
@@ -166,7 +166,7 @@ FSGNJN.D, and FSGNJX.D are defined analogously to the single-precision
 sign-injection instruction.
 //FSGNJ.D, FSGNJN.D, and FSGNJX.D
 
-include::images/wavedrom/fsjgnjnx-d.adoc[]
+include::images/wavedrom/fsjgnjnx-d.edn[]
 //.Double-precision sign-injection
 
 For XLEN&#8805;64 only, instructions are provided to move bit
@@ -180,7 +180,7 @@ register _rd_.
 FMV.X.D and FMV.D.X do not modify the bits being transferred; in
 particular, the payloads of non-canonical NaNs are preserved.
 
-include::images/wavedrom/d-xwwx.adoc[]
+include::images/wavedrom/d-xwwx.edn[]
 [[fmvxddx]]
 //.Double-precision float move to _rd_
 
@@ -214,7 +214,7 @@ analogously to their single-precision counterparts, but operate on
 double-precision operands.
 (((floating-point, compare)))
 
-include::images/wavedrom/double-fl-compare.adoc[]
+include::images/wavedrom/double-fl-compare.edn[]
 [[fl-compare]]
 //.Double-precision float compare
 
@@ -225,8 +225,6 @@ defined analogously to its single-precision counterpart, but operates on
 double-precision operands.
 (((floating-point, classify)))
 
-include::images/wavedrom/double-fl-class.adoc[]
+include::images/wavedrom/double-fl-class.edn[]
 [[fl-class]]
 //.Double-precision float classify
-
-
diff --git a/src/f-st-ext.adoc b/src/f-st-ext.adoc
@@ -87,7 +87,7 @@ operations and holds the accrued exception flags, as shown in <<fcsr>>.
 
 [[fcsr, Floating-Point Control and Status Register]]
 .Floating-point control and status register
-include::images/wavedrom/float-csr.adoc[]
+include::images/wavedrom/float-csr.edn[]
 
 The `fcsr` register can be read and written with the FRCSR and FSCSR
 instructions, which are assembler pseudoinstructions built on the

diff --git a/src/images/wavedrom/d-xwwx.adoc → src/images/wavedrom/d-xwwx.edn b/src/images/wavedrom/d-xwwx.adoc → src/images/wavedrom/d-xwwx.edn
diff --git a/src/images/wavedrom/division-op.adoc → src/images/wavedrom/division-op.edn b/src/images/wavedrom/division-op.adoc → src/images/wavedrom/division-op.edn
diff --git a/src/images/wavedrom/double-fl-class.adoc → src/images/wavedrom/double-fl-class.edn b/src/images/wavedrom/double-fl-class.adoc → src/images/wavedrom/double-fl-class.edn
diff --git a/src/images/wavedrom/double-fl-compare.adoc → src/images/wavedrom/double-fl-compare.edn b/src/images/wavedrom/double-fl-compare.adoc → src/images/wavedrom/double-fl-compare.edn
diff --git a/src/images/wavedrom/double-fl-compute.adoc → src/images/wavedrom/double-fl-compute.edn b/src/images/wavedrom/double-fl-compute.adoc → src/images/wavedrom/double-fl-compute.edn
diff --git a/...images/wavedrom/double-fl-convert-mv.adoc → src/images/wavedrom/double-fl-convert-mv.edn b/...images/wavedrom/double-fl-convert-mv.adoc → src/images/wavedrom/double-fl-convert-mv.edn
diff --git a/src/images/wavedrom/double-ls.adoc → src/images/wavedrom/double-ls.edn b/src/images/wavedrom/double-ls.adoc → src/images/wavedrom/double-ls.edn
diff --git a/src/images/wavedrom/env_call-breakpoint.adoc → src/images/wavedrom/env-call-breakpoint.edn b/src/images/wavedrom/env_call-breakpoint.adoc → src/images/wavedrom/env-call-breakpoint.edn
diff --git a/src/images/wavedrom/fcvt-sd-ds.adoc → src/images/wavedrom/fcvt-sd-ds.edn b/src/images/wavedrom/fcvt-sd-ds.adoc → src/images/wavedrom/fcvt-sd-ds.edn
diff --git a/src/images/wavedrom/float-csr.adoc → src/images/wavedrom/float-csr.edn b/src/images/wavedrom/float-csr.adoc → src/images/wavedrom/float-csr.edn
diff --git a/src/images/wavedrom/flt-pt-to-int-move.adoc → src/images/wavedrom/flt-pt-to-int-move.edn b/src/images/wavedrom/flt-pt-to-int-move.adoc → src/images/wavedrom/flt-pt-to-int-move.edn
diff --git a/...es/wavedrom/flt-to-flt-sgn-inj-instr.adoc → ...ges/wavedrom/flt-to-flt-sgn-inj-instr.edn b/...es/wavedrom/flt-to-flt-sgn-inj-instr.adoc → ...ges/wavedrom/flt-to-flt-sgn-inj-instr.edn
diff --git a/src/images/wavedrom/fnmaddsub.adoc → src/images/wavedrom/fnmaddsub.edn b/src/images/wavedrom/fnmaddsub.adoc → src/images/wavedrom/fnmaddsub.edn
diff --git a/src/images/wavedrom/fsjgnjnx-d.adoc → src/images/wavedrom/fsjgnjnx-d.edn b/src/images/wavedrom/fsjgnjnx-d.adoc → src/images/wavedrom/fsjgnjnx-d.edn
diff --git a/src/images/wavedrom/half-ls.adoc → src/images/wavedrom/half-ls.edn b/src/images/wavedrom/half-ls.adoc → src/images/wavedrom/half-ls.edn
diff --git a/...images/wavedrom/half-pr-flt-pt-class.adoc → src/images/wavedrom/half-pr-flt-pt-class.edn b/...images/wavedrom/half-pr-flt-pt-class.adoc → src/images/wavedrom/half-pr-flt-pt-class.edn
diff --git a/...ages/wavedrom/half-pr-flt-pt-compare.adoc → ...mages/wavedrom/half-pr-flt-pt-compare.edn b/...ages/wavedrom/half-pr-flt-pt-compare.adoc → ...mages/wavedrom/half-pr-flt-pt-compare.edn
diff --git a/...mages/wavedrom/half-prec-conv-and-mv.adoc → ...images/wavedrom/half-prec-conv-and-mv.edn b/...mages/wavedrom/half-prec-conv-and-mv.adoc → ...images/wavedrom/half-prec-conv-and-mv.edn
diff --git a/...wavedrom/half-prec-flpt-to-flpt-conv.adoc → .../wavedrom/half-prec-flpt-to-flpt-conv.edn b/...wavedrom/half-prec-flpt-to-flpt-conv.adoc → .../wavedrom/half-prec-flpt-to-flpt-conv.edn
diff --git a/src/images/wavedrom/half-store.adoc → src/images/wavedrom/half-store.edn b/src/images/wavedrom/half-store.adoc → src/images/wavedrom/half-store.edn
diff --git a/src/images/wavedrom/hint-nopv_rv32i.adoc → src/images/wavedrom/hint-nopv_rv32i.edn b/src/images/wavedrom/hint-nopv_rv32i.adoc → src/images/wavedrom/hint-nopv_rv32i.edn
diff --git a/src/images/wavedrom/hint-nopv_rv64i.adoc → src/images/wavedrom/hint-nopv_rv64i.edn b/src/images/wavedrom/hint-nopv_rv64i.adoc → src/images/wavedrom/hint-nopv_rv64i.edn
diff --git a/src/images/wavedrom/immediate_variants.adoc → src/images/wavedrom/immediate-variants.edn b/src/images/wavedrom/immediate_variants.adoc → src/images/wavedrom/immediate-variants.edn
diff --git a/src/images/wavedrom/immediate.adoc → src/images/wavedrom/immediate.edn b/src/images/wavedrom/immediate.adoc → src/images/wavedrom/immediate.edn
diff --git a/src/images/wavedrom/instruction_formats.adoc → src/images/wavedrom/instruction-formats.edn b/src/images/wavedrom/instruction_formats.adoc → src/images/wavedrom/instruction-formats.edn
diff --git a/src/images/wavedrom/int-comp-lui-aiupc.adoc → src/images/wavedrom/int-comp-lui-aiupc.edn b/src/images/wavedrom/int-comp-lui-aiupc.adoc → src/images/wavedrom/int-comp-lui-aiupc.edn
diff --git a/...ges/wavedrom/int-comp-slli-srli-srai.adoc → ...ages/wavedrom/int-comp-slli-srli-srai.edn b/...ges/wavedrom/int-comp-slli-srli-srai.adoc → ...ages/wavedrom/int-comp-slli-srli-srai.edn
diff --git a/src/images/wavedrom/int_reg-reg.adoc → src/images/wavedrom/int-reg-reg.edn b/src/images/wavedrom/int_reg-reg.adoc → src/images/wavedrom/int-reg-reg.edn
diff --git a/...mages/wavedrom/integer_computational.adoc → ...images/wavedrom/integer-computational.edn b/...mages/wavedrom/integer_computational.adoc → ...images/wavedrom/integer-computational.edn
diff --git a/...wavedrom/load-reserve-st-conditional.adoc → .../wavedrom/load-reserve-st-conditional.edn b/...wavedrom/load-reserve-st-conditional.adoc → .../wavedrom/load-reserve-st-conditional.edn
diff --git a/src/images/wavedrom/load_store.adoc → src/images/wavedrom/load-store.edn b/src/images/wavedrom/load_store.adoc → src/images/wavedrom/load-store.edn
diff --git a/...mages/wavedrom/m-st-ext-for-int-mult.adoc → ...images/wavedrom/m-st-ext-for-int-mult.edn b/...mages/wavedrom/m-st-ext-for-int-mult.adoc → ...images/wavedrom/m-st-ext-for-int-mult.edn
diff --git a/src/images/wavedrom/mem_order.adoc → src/images/wavedrom/mem-order.edn b/src/images/wavedrom/mem_order.adoc → src/images/wavedrom/mem-order.edn
diff --git a/src/images/wavedrom/menvcfgreg.adoc → src/images/wavedrom/menvcfgreg.edn b/src/images/wavedrom/menvcfgreg.adoc → src/images/wavedrom/menvcfgreg.edn
diff --git a/src/images/wavedrom/mm-env-call.adoc → src/images/wavedrom/mm-env-call.edn b/src/images/wavedrom/mm-env-call.adoc → src/images/wavedrom/mm-env-call.edn
diff --git a/src/images/wavedrom/mop-r.adoc → src/images/wavedrom/mop-r.edn b/src/images/wavedrom/mop-r.adoc → src/images/wavedrom/mop-r.edn
diff --git a/src/images/wavedrom/mop-rr.adoc → src/images/wavedrom/mop-rr.edn b/src/images/wavedrom/mop-rr.adoc → src/images/wavedrom/mop-rr.edn
diff --git a/src/images/wavedrom/mseccfg.adoc → src/images/wavedrom/mseccfg.edn b/src/images/wavedrom/mseccfg.adoc → src/images/wavedrom/mseccfg.edn
diff --git a/src/images/wavedrom/mstatushreg.adoc → src/images/wavedrom/mstatushreg.edn b/src/images/wavedrom/mstatushreg.adoc → src/images/wavedrom/mstatushreg.edn
diff --git a/src/images/wavedrom/mstatusreg-rv321.adoc → src/images/wavedrom/mstatusreg-rv321.edn b/src/images/wavedrom/mstatusreg-rv321.adoc → src/images/wavedrom/mstatusreg-rv321.edn
diff --git a/src/images/wavedrom/mstatusreg.adoc → src/images/wavedrom/mstatusreg.edn b/src/images/wavedrom/mstatusreg.adoc → src/images/wavedrom/mstatusreg.edn
diff --git a/src/images/wavedrom/nop-v.adoc → src/images/wavedrom/nop-v.edn b/src/images/wavedrom/nop-v.adoc → src/images/wavedrom/nop-v.edn
diff --git a/src/images/wavedrom/nop.adoc → src/images/wavedrom/nop.edn b/src/images/wavedrom/nop.adoc → src/images/wavedrom/nop.edn
diff --git a/src/m-st-ext.adoc b/src/m-st-ext.adoc
@@ -15,7 +15,7 @@ accelerators.
 
 === Multiplication Operations
 
-include::images/wavedrom/m-st-ext-for-int-mult.adoc[]
+include::images/wavedrom/m-st-ext-for-int-mult.edn[]
 [[m-st-ext-for-int-mult]]
 //.Multiplication operation instructions
 (((MUL, MULH)))
@@ -52,7 +52,7 @@ to shift both arguments left by 32 bits, then use MULH[[S]U].
 
 === Division Operations
 
-include::images/wavedrom/division-op.adoc[]
+include::images/wavedrom/division-op.edn[]
 [[division-op]]
 //.Division operation instructions
 (((MUL, DIV)))

diff --git a/src/machine.adoc b/src/machine.adoc
@@ -368,18 +368,18 @@ S-level ISA.
 
 [[mstatusreg-rv32]]
 .Machine-mode status (`mstatus`) register for RV32
-include::images/wavedrom/mstatusreg-rv321.adoc[]
+include::images/wavedrom/mstatusreg-rv321.edn[]
 
 [[mstatusreg]]
 .Machine-mode status (`mstatus`) register for RV64
-include::images/wavedrom/mstatusreg.adoc[]
+include::images/wavedrom/mstatusreg.edn[]
 
 For RV32 only, `mstatush` is a 32-bit read/write register formatted as
 shown in <<mstatushreg>>. Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.
 
 [[mstatushreg]]
 .Additional machine-mode status (`mstatush`) register  for RV32.
-include::images/wavedrom/mstatushreg.adoc[]
+include::images/wavedrom/mstatushreg.edn[]
 
 [[privstack]]
 ===== Privilege and Global Interrupt-Enable Stack in `mstatus` register
@@ -2100,7 +2100,7 @@ privileged than M.
 
 [[menvcfgreg]]
 .Machine environment configuration (`menvcfg`) register.
-include::images/wavedrom/menvcfgreg.adoc[]
+include::images/wavedrom/menvcfgreg.edn[]
 
 
 If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`,
@@ -2227,7 +2227,7 @@ shown in <<mseccfg>>, that controls security features.
 
 [[mseccfg]]
 .Machine security configuration (`mseccfg`) register.
-include::images/wavedrom/mseccfg.adoc[]
+include::images/wavedrom/mseccfg.edn[]
 
 The definitions of the SSEED and USEED fields will be furnished by the
 forthcoming entropy-source extension, Zkr. Their allocations within
@@ -2348,7 +2348,7 @@ eventually, but not necessarily immediately.
 
 ==== Environment Call and Breakpoint
 
-include::images/wavedrom/mm-env-call.adoc[]
+include::images/wavedrom/mm-env-call.edn[]
 
 The ECALL instruction is used to make a request to the supporting
 execution environment. When executed in U-mode, S-mode, or M-mode, it

diff --git a/src/rv32.adoc b/src/rv32.adoc
@@ -174,7 +174,7 @@ bits in the instruction and have been allocated to reduce hardware
 complexity. In particular, the sign bit for all immediates is always in
 bit 31 of the instruction to speed sign-extension circuitry.
 
-include::images/wavedrom/instruction_formats.adoc[]
+include::images/wavedrom/instruction-formats.edn[]
 [[base_instr,Base instruction formats]]
 RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction's immediate field as is usually done.
 
@@ -201,7 +201,7 @@ to keep the ISA as simple as possible.
 There are a further two variants of the instruction formats (B/J) based
 on the handling of immediates, as shown in <<baseinstformatsimm>>.
 
-include::images/wavedrom/immediate_variants.adoc[]
+include::images/wavedrom/immediate-variants.edn[]
 [[baseinstformatsimm,Base instruction formats immediate variants.]]
 //.RISC-V base instruction formats showing immediate variants.
 
@@ -224,7 +224,7 @@ each of the base instruction formats, and is labeled to show which
 instruction bit (inst[_y_]) produces each bit of the immediate value.
 [[immtypes, Immediate types]]
 .Types of immediate produced by RISC-V instructions. 
-include::images/wavedrom/immediate.adoc[]
+include::images/wavedrom/immediate.edn[]
 
 The fields are labeled with the instruction bits used to construct their value.  Sign extensions always uses inst[31].
 
@@ -291,7 +291,7 @@ comparing the results of ADD and ADDW on the operands.
 
 ==== Integer Register-Immediate Instructions
 
-include::images/wavedrom/integer_computational.adoc[]
+include::images/wavedrom/integer-computational.edn[]
 //.Integer Computational Instructions
 
 ADDI adds the sign-extended 12-bit immediate to register _rs1_.
@@ -312,7 +312,7 @@ XOR on register _rs1_ and the sign-extended 12-bit immediate and place
 the result in _rd_. Note, XORI _rd, rs1, -1_ performs a bitwise logical
 inversion of register _rs1_ (assembler pseudoinstruction NOT _rd, rs_).
 
-include::images/wavedrom/int-comp-slli-srli-srai.adoc[]
+include::images/wavedrom/int-comp-slli-srli-srai.edn[]
 [[int-comp-slli-srli-srai]]
 //.Integer register-immediate, SLLI, SRLI, SRAI
 
@@ -324,7 +324,7 @@ shifted into the lower bits); SRLI is a logical right shift (zeros are
 shifted into the upper bits); and SRAI is an arithmetic right shift (the
 original sign bit is copied into the vacated upper bits).
 
-include::images/wavedrom/int-comp-lui-aiupc.adoc[]
+include::images/wavedrom/int-comp-lui-aiupc.edn[]
 [[int-comp-lui-aiupc]]
 //.Integer register-immediate, U-immediate
 
@@ -364,7 +364,7 @@ the _rs1_ and _rs2_ registers as source operands and write the result
 into register _rd_. The _funct7_ and _funct3_ fields select the type of
 operation.
 
-include::images/wavedrom/int_reg-reg.adoc[]
+include::images/wavedrom/int-reg-reg.edn[]
 [[int-reg-reg]]
 //.Integer register-register
 
@@ -383,7 +383,7 @@ the lower 5 bits of register _rs2_.
 
 ==== NOP Instruction
 
-include::images/wavedrom/nop.adoc[]
+include::images/wavedrom/nop.edn[]
 [[nop]]
 //.NOP instructions
 
@@ -692,7 +692,7 @@ significance. Loads similarly transfer the contents of the greater
 memory byte addresses to the less-significant register bytes.
 ====
 
-include::images/wavedrom/load_store.adoc[]
+include::images/wavedrom/load-store.edn[]
 [[load-store,load and store]]
 //.Load and store instructions
 
@@ -781,7 +781,7 @@ are aligned.
 [[fence]]
 === Memory Ordering Instructions
 
-include::images/wavedrom/mem_order.adoc[]
+include::images/wavedrom/mem-order.edn[]
 [[mem-order]]
 //.Memory ordering instructions
 
@@ -890,7 +890,7 @@ implementations might execute more of each system instruction in
 hardware.
 ====
 
-include::images/wavedrom/env_call-breakpoint.adoc[]
+include::images/wavedrom/env-call-breakpoint.edn[]
 [[env-call]]
 //.Environment call and breakpoint instructions
 

diff --git a/src/rv64.adoc b/src/rv64.adoc
@@ -136,7 +136,7 @@ results to 64 bits. The shift amount is given by _rs2[4:0]_.
 RV64I extends the address space to 64 bits. The execution environment
 will define what portions of the address space are legal to access.
 
-include::images/wavedrom/load_store.adoc[]
+include::images/wavedrom/load-store.edn[]
 [[load_store]]
 //.Load and store instructions
 

diff --git a/src/zfh.adoc b/src/zfh.adoc
@@ -75,7 +75,7 @@ FCVT.WU.H, FCVT.LU.H, FCVT.H.WU, and FCVT.H.LU variants convert to or
 from unsigned integer values. FCVT.L[U].H and FCVT.H.L[U] are RV64-only
 instructions.
 
-include::images/wavedrom/half-prec-conv-and-mv.adoc[]
+include::images/wavedrom/half-prec-conv-and-mv.edn[]
 [[half-prec-conv-and-mv]]
 
 New floating-point-to-floating-point conversion instructions are added.
@@ -90,14 +90,14 @@ is present, FCVT.Q.H or FCVT.H.Q converts a half-precision
 floating-point number to a quad-precision floating-point number, or
 vice-versa, respectively.
 
-include::images/wavedrom/half-prec-flpt-to-flpt-conv.adoc[]
+include::images/wavedrom/half-prec-flpt-to-flpt-conv.edn[]
 [[half-prec-flpt-to-flpt-conv]]
 
 Floating-point to floating-point sign-injection instructions, FSGNJ.H,
 FSGNJN.H, and FSGNJX.H are defined analogously to the single-precision
 sign-injection instruction.
 
-include::images/wavedrom/flt-to-flt-sgn-inj-instr.adoc[]
+include::images/wavedrom/flt-to-flt-sgn-inj-instr.edn[]
 [[flt-to-flt-sgn-inj-instr]]
 
 Instructions are provided to move bit patterns between the
@@ -113,7 +113,7 @@ floating-point register _rd_, NaN-boxing the result.
 FMV.X.H and FMV.H.X do not modify the bits being transferred; in
 particular, the payloads of non-canonical NaNs are preserved.
 
-include::images/wavedrom/flt-pt-to-int-move.adoc[]
+include::images/wavedrom/flt-pt-to-int-move.edn[]
 [[flt-pt-to-int-move]]
 
 === Half-Precision Floating-Point Compare Instructions
@@ -122,7 +122,7 @@ The half-precision floating-point compare instructions are defined
 analogously to their single-precision counterparts, but operate on
 half-precision operands.
 
-include::images/wavedrom/half-pr-flt-pt-compare.adoc[]
+include::images/wavedrom/half-pr-flt-pt-compare.edn[]
 [[half-pr-flt-pt-compare]]
 
 === Half-Precision Floating-Point Classify Instruction
@@ -131,7 +131,7 @@ The half-precision floating-point classify instruction, FCLASS.H, is
 defined analogously to its single-precision counterpart, but operates on
 half-precision operands.
 
-include::images/wavedrom/half-pr-flt-pt-class.adoc[]
+include::images/wavedrom/half-pr-flt-pt-class.edn[]
 [[half-pr-flt-class]]
 
 === "Zfhmin" Standard Extension for Minimal Half-Precision Floating-Point

diff --git a/src/zimop.adoc b/src/zimop.adoc
@@ -32,7 +32,7 @@ Unless redefined by another extension, these instructions simply write 0 to
 `x[rd]`.  Their encoding allows future extensions to define them to read `x[rs1]`,
 as well as write `x[rd]`.
 
-include::images/wavedrom/mop-r.adoc[]
+include::images/wavedrom/mop-r.edn[]
 [[mop-r]]
 
 The Zimop extension additionally defines 8 MOP instructions named
@@ -41,7 +41,7 @@ Unless redefined by another extension, these instructions simply
 write 0 to `x[rd]`.  Their encoding allows future extensions to define them to
 read `x[rs1]` and `x[rs2]`, as well as write `x[rd]`.
 
-include::images/wavedrom/mop-rr.adoc[]
+include::images/wavedrom/mop-rr.edn[]
 [[mop-rr]]
 
 NOTE: The recommended assembly syntax for MOP.R.__n__ is MOP.R.__n__ rd, rs1,