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More register name clean up #1357

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More register name clean up #1357

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58 changes: 29 additions & 29 deletions src/machine.adoc
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Expand Up @@ -53,7 +53,7 @@ knowing the register width (MXLEN) of the hart. The base width is
given by __MXLEN=2^MXL+4^__.

The base width can also be found if `misa` is zero, by placing the
immediate 4 in a register then shifting the register left by 31 bits at
immediate 4 in a register and then shifting the register left by 31 bits at
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a time. If zero after one shift, then the hart is RV32. If zero after
two shifts, then the hart is RV64, else RV128.
====
Expand Down Expand Up @@ -285,7 +285,7 @@ is not implemented. The combination of `mvendorid` and `marchid` should
uniquely identify the type of hart microarchitecture that is
implemented.

.Machine Architecture ID register (`marchid`)
.Machine Architecture ID (`marchid`) register
include::images/bytefield/marchid.adoc[]

Open-source project architecture IDs are allocated globally by RISC-V
Expand Down Expand Up @@ -323,7 +323,7 @@ implementation, but a value of 0 can be returned to indicate that the
field is not implemented. The Implementation value should reflect the
design of the RISC-V processor itself and not any surrounding system.

.Machine Implementation ID register (`mimpid`)
.Machine Implementation ID (`mimpid`) register
include::images/bytefield/mimpid.adoc[]

[NOTE]
Expand All @@ -345,7 +345,7 @@ numbered contiguously in a multiprocessor system, but at least one hart
must have a hart ID of zero. Hart IDs must be unique within the
execution environment.

.Hart ID register (`mhartid`)
.Hart ID (`mhartid`) register
include::images/bytefield/mhartid.adoc[]

[NOTE]
Expand All @@ -367,20 +367,20 @@ restricted view of `mstatus` appears as the `sstatus` register in the
S-level ISA.

[[mstatusreg-rv32]]
.Machine-mode status register (`mstatus`) for RV32
.Machine-mode status (`mstatus`) register for RV32
include::images/bytefield/mstatusreg-rv32.adoc[]

include::images/bytefield/mstatusreg.adoc[]
[[mstatusreg]]
.Machine-mode status register (`mstatus`) for RV64
.Machine-mode status (`mstatus`) register for RV64
include::images/bytefield/mstatusreg2.adoc[]


For RV32 only, `mstatush` is a 32-bit read/write register formatted as
shown in <<mstatushreg>>. Bits 30:4 of `mstatush` generally contain the same fields found in bits 62:36 of `mstatus` for RV64. Fields SD, SXL, and UXL do not exist in `mstatush`.

[[mstatushreg]]
.Additional machine-mode status register (`mstatush`) for RV32.
.Additional machine-mode status (`mstatush`) register for RV32.
include::images/bytefield/mstatushreg.adoc[]

[[privstack]]
Expand Down Expand Up @@ -1142,7 +1142,7 @@ implementations can provide individual read/write bits within `medeleg`
and `mideleg` to indicate that certain exceptions and interrupts should
be processed directly by a lower privilege level. The machine exception
delegation register (`medeleg`) is a 64-bit read/write register.
The machine interrupt delegation register (`mideleg`) is an MXLEN-bit
The machine interrupt delegation (`mideleg`) register is an MXLEN-bit
read/write register.

In harts with S-mode, the `medeleg` and `mideleg` registers must
Expand Down Expand Up @@ -1202,7 +1202,7 @@ will not be taken when executing in M-mode. By contrast, if `mideleg`[5]
is clear, STIs can be taken in any mode and regardless of current mode
will transfer control to M-mode.

.Machine Exception Delegation Register `medeleg`.
.Machine Exception Delegation (`medeleg`) register.
include::images/bytefield/medeleg.adoc[]

`medeleg` has a bit position allocated for every synchronous exception
Expand All @@ -1213,9 +1213,9 @@ lower-privilege trap handler).

When XLEN=32, `medelegh` is a 32-bit read/write register
that aliases bits 63:32 of `medeleg`.
Register `medelegh` does not exist when XLEN=64.
The `medelegh` register does not exist when XLEN=64.

.Machine Interrupt Delegation Register `mideleg`.
.Machine Interrupt Delegation (`mideleg`) Register.
include::images/bytefield/mideleg.adoc[]

`mideleg` holds trap delegation bits for individual interrupts, with the
Expand All @@ -1239,10 +1239,10 @@ bits 16 and above are designated for platform use.
NOTE: Interrupts designated for platform use may be designated for custom use
at the platform's discretion.

.Machine Interrupt-Pending Register (mip).
.Machine Interrupt-Pending (`mip`) register.
include::images/bytefield/mideleg.adoc[]

.Machine Interrupt-Enable Register (mie)
.Machine Interrupt-Enable (`mie`) register
include::images/bytefield/mideleg.adoc[]

An interrupt _i_ will trap to M-mode (causing the privilege mode to
Expand Down Expand Up @@ -1272,7 +1272,7 @@ A bit in `mie` must be writable if the corresponding interrupt can ever
become pending. Bits of `mie` that are not writable must be read-only
zero.

The standard portions (bits 15:0) of registers `mip` and `mie` are
The standard portions (bits 15:0) of the `mip` and `mie` registers are
formatted as shown in <<mipreg-standard>> and <<miereg-standard>> respectively.

[[mipreg-standard]]
Expand Down Expand Up @@ -1304,7 +1304,7 @@ interrupt controller.

Bits `mip`.MTIP and `mie`.MTIE are the interrupt-pending and
interrupt-enable bits for machine timer interrupts. MTIP is read-only in
`mip`, and is cleared by writing to the memory-mapped machine-mode timer
the `mip` register, and is cleared by writing to the memory-mapped machine-mode timer
compare register.

Bits `mip`.MSIP and `mie`.MSIE are the interrupt-pending and
Expand Down Expand Up @@ -1454,11 +1454,11 @@ The `mhpmevent__n__h` CSRs are provided only if the Sscofpmf extension is implem
[[mcounteren]]
==== Machine Counter-Enable (`mcounteren`) Register

The counter-enable register `mcounteren` is a 32-bit register that
The counter-enable `mcounteren` register is a 32-bit register that
controls the availability of the hardware performance-monitoring
counters to the next-lower privileged mode.

.Counter-enable register (`mcounteren`).
.Counter-enable (`mcounteren`) register.
include::images/bytefield/counteren.adoc[]

The settings in this register only control accessibility. The act of
Expand Down Expand Up @@ -1506,7 +1506,7 @@ executing in a less-privileged mode. In harts without U-mode, the

==== Machine Counter-Inhibit (`mcountinhibit`) Register

.Counter-inhibit register `mcountinhibit`
.Counter-inhibit `mcountinhibit` register
include::images/bytefield/counterinh.adoc[]

The counter-inhibit register `mcountinhibit` is a 32-bit *WARL* register that
Expand Down Expand Up @@ -1565,7 +1565,7 @@ design, the OS can rely on holding a value in the `mscratch` register
while the user context is running.
====

==== Machine Exception Program Counter (`mepc`)
==== Machine Exception Program Counter (`mepc`) Register

`mepc` is an MXLEN-bit read/write register formatted as shown in
<<mepcreg>>. The low bit of `mepc` (`mepc[0]`) is
Expand Down Expand Up @@ -1617,7 +1617,7 @@ the possible machine-level exception codes. The Exception Code is a
*WLRL* field, so is only guaranteed to hold supported exception codes.

[[mcausereg]]
.Machine Cause register `mcause`.
.Machine Cause (`mcause`) register.
include::images/bytefield/mcausereg.adoc[]

Note that load and load-reserved instructions generate load exceptions,
Expand Down Expand Up @@ -1649,7 +1649,7 @@ synchronous exceptions is implementation-defined.
<<<

[[mcauses]]
.Machine cause register (mcause) values after trap.
.Machine cause (`mcause`) register values after trap.
[%autowidth,float="center",align="center",cols=">,>,<",options="header",]
|===
|Interrupt |Exception Code |Description
Expand Down Expand Up @@ -1889,7 +1889,7 @@ exceptions. This design reduces datapath cost for most implementations,
particularly those with hardware page-table walkers.

[[mtvalreg]]
.Machine Trap Value register.
.Machine Trap Value (`mtval`) register.
include::images/bytefield/mtvalreg.adoc[]


Expand Down Expand Up @@ -1956,14 +1956,14 @@ _N_ is the smaller of MXLEN and ILEN.

==== Machine Configuration Pointer (`mconfigptr`) Register

`mconfigptr` is an MXLEN-bit read-only CSR, formatted as shown in
The `mconfigptr` register is an MXLEN-bit read-only CSR, formatted as shown in
<<mconfigptrreg>>, that holds the physical
address of a configuration data structure. Software can traverse this
data structure to discover information about the harts, the platform,
and their configuration.

[[mconfigptrreg]]
.Machine Configuration Pointer register.
.Machine Configuration Pointer (`mconfigptr`) register.
include::images/bytefield/mconfigptrreg.adoc[]


Expand All @@ -1972,7 +1972,7 @@ i.e., if MXLEN is
latexmath:[$8\times n$], then `mconfigptr`[latexmath:[$\log_2n$]-1:0]
must be zero.

`mconfigptr` must be implemented, but it may be zero to indicate the
The `mconfigptr` register must be implemented, but it may be zero to indicate the
configuration data structure does not exist or that an alternative
mechanism must be used to locate it.

Expand All @@ -1983,7 +1983,7 @@ standardized.

***

While `mconfigptr` will simply be hardwired in some implementations,
While the `mconfigptr` register will simply be hardwired in some implementations,
other implementations may provide a means to configure the value
returned on CSR reads. For example, `mconfigptr` might present the value
of a memory-mapped register that is programmed by the platform or by
Expand All @@ -1999,7 +1999,7 @@ certain characteristics of the execution environment for modes less
privileged than M.

[#menvcfgreg]
.Machine environment configuration register (`menvcfg`).
.Machine environment configuration (`menvcfg`) register.
include::images/bytefield/menvcfgreg.adoc[]

If bit FIOM (Fence of I/O implies Memory) is set to one in `menvcfg`,
Expand Down Expand Up @@ -2093,7 +2093,7 @@ ratification of that extension.

When XLEN=32, `menvcfgh` is a 32-bit read/write register
that aliases bits 63:32 of `menvcfg`.
Register `menvcfgh` does not exist when XLEN=64.
The `menvcfgh` register does not exist when XLEN=64.

If U-mode is not supported, then registers `menvcfg` and `menvcfgh` do
not exist.
Expand All @@ -2104,7 +2104,7 @@ not exist.
shown in <<mseccfg>>, that controls security features.

[[mseccfg]]
.Machine security configuration register (`mseccfg`).
.Machine security configuration (`mseccfg`) register.
include::images/bytefield/mseccfg.adoc[]

The definitions of the SSEED and USEED fields will be furnished by the
Expand Down