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Make vector CSR titles more consistent and remove some trailing spaces #1439

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Jun 1, 2024
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Make vector CSR titles more consistent and remove some trailing spaces #1439

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14 changes: 7 additions & 7 deletions src/v-st-ext.adoc
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
[[vector]]
== "V" Standard Extension for Vector Operations, Version 1.0
== "V" Standard Extension for Vector Operations, Version 1.0

[NOTE]
====
Expand Down Expand Up @@ -180,7 +180,7 @@ is anticipated that a future extended 64-bit instruction encoding
would allow these fields to be specified statically in the instruction
encoding.

===== Vector selected element width `vsew[2:0]`
===== Vector Selected Element Width (`vsew[2:0]`)

The value in `vsew` sets the dynamic _selected_ _element_ _width_
(SEW). By default, a vector register is viewed as being divided into
Expand Down Expand Up @@ -452,7 +452,7 @@ when it cares about the non-participating elements, but given the
historical meaning of the instruction prior to introduction of these
flags, it was decided to always require them in future assembly code.

===== Vector Type Illegal `vill`
===== Vector Type Illegal (`vill`)

The `vill` bit is used to encode that a previous `vset{i}vl{i}`
instruction attempted to write an unsupported value to `vtype`.
Expand Down Expand Up @@ -602,7 +602,7 @@ roundoff_signed(v, d) = (signed(v) >> d) + r
----
are used to represent this operation in the instruction descriptions below.

==== Vector Fixed-Point Saturation Flag `vxsat`
==== Vector Fixed-Point Saturation Flag (`vxsat`)

The `vxsat` CSR has a single read-write least-significant bit
(`vxsat[0]`) that indicates if a fixed-point instruction has had to
Expand Down Expand Up @@ -843,7 +843,7 @@ that it can be aligned with the other datawidths in the same column
that also have an LMUL setting, such that all have the same VLMAX.

|===
| 7+^| SEW/LMUL
| 7+^| SEW/LMUL
| | 1 | 2 | 4 | 8 | 16 | 32 | 64

| SEW= 8 | 8 | 4 | 2 | 1 | 1/2 | 1/4 | 1/8
Expand Down Expand Up @@ -1733,7 +1733,7 @@ can be used to probe for valid effective addresses. The unit-stride
versions only allow probing a region immediately contiguous to a known
region, and so reduce the security impact when used in unprivileged
code. However, code running in S-mode can establish arbitrary page
translations that allow probing of random guest physical addresses
translations that allow probing of random guest physical addresses
provided by a hypervisor. Strided and scatter/gather fault-only-first
instructions are not provided due to lack of encoding space, but they
can also represent a larger security hole, allowing even unprivileged
Expand Down Expand Up @@ -5063,7 +5063,7 @@ All Zve* extensions support all vector mask instructions (Section
<<sec-vector-mask>>).

All Zve* extensions support all vector permutation instructions
(Section <<sec-vector-permute>>), except that Zve32x and Zve64x
(Section <<sec-vector-permute>>), except that Zve32x and Zve64x
do not include those with floating-point operands, and Zve64f does not include those
with EEW=64 floating-point operands.

Expand Down
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