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Removed paragraph that detailed the trap behavior #40

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Jul 4, 2024
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Removed paragraph that detailed the trap behavior #40

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2 changes: 0 additions & 2 deletions zilsd.adoc
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Expand Up @@ -89,8 +89,6 @@ When using `x0` as `src` of SD or C.SDSP, the entire 64-bit operand is zero —

In implementations that crack Zilsd instructions for sequential execution, correct execution requires addressing idempotent memory, because the hart must be able to handle traps detected during the sequence. The entire sequence is re-executed after returning from the trap handler, and multiple traps are possible during the sequence.

If a trap occurs during the sequence then xEPC is updated with the PC of the instruction, xTVAL (if not read-only-zero) updated with the bad address if it was an access fault and xCAUSE updated with the type of trap.

[NOTE]
====
It is implementation defined whether interrupts can also be taken during the sequence execution.
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