Release 1.0-rc3

What's Changed

• Fixed a typo by @christian-herber-nxp in #57

Full Changelog: v1.0-rc2...v1.0-rc3

Release 1.0-rc2

What's Changed

• Relaxed the requirement regarding atomic override of destination registers for LD to allow more implementation options by @christian-herber-nxp in #53

Full Changelog: v1.0-rc1...v1.0-rc2

Release 1.0-rc1

What's Changed

• Preparing document for first release candidate by @christian-herber-nxp in #52

Full Changelog: v0.10...v1.0-rc1

Release 0.10

What's Changed

• Replaced the term core with hart by @christian-herber-nxp in #30
• Replaced simm und uimm with offset by @christian-herber-nxp in #41
• Removed paragraph that detailed the trap behavior by @christian-herber-nxp in #40
• Reworded statement on reusing RV64 instruction encodings by @christian-herber-nxp in #39
• Removed section on non-idempotent memory handling by @christian-herber-nxp in #38
• Renaming Zcmlsd to Zclsd by @christian-herber-nxp in #42
• Added requirement for 4B accesses to be atomic if 4B aligned by @christian-herber-nxp in #43
• Contribute ARC feedback on Zilsd by @aswaterman in #45

Release 0.9.0

v0.9.0

Updating document to stable state

Release 0.8.1

v0.8.1

Merge pull request #11 from riscv/compressed-encodings-into-separate-…

Release 0.8.0

v0.8.0

Merge pull request #6 from riscv/5-scaled-offsets-for-compressed-enco…