Priv 1.10 should use *tval instead of *badaddr

[msuozzo]

From the Priv 1.10 preface:

The 'mbadaddr' register has been subsumed by a more
general 'mtval' register that can now capture bad
instruction bits on an illegal instruction fault to speed
instruction emulation.

While mtval (Section 3.1.21) has been added (link), it isn't used yet (link). stval (Section 4.1.11) is neither present nor used and it appears to be included in the Priv 1.10 spec (although it isn't mentioned in the change notes).

Also, the Priv 1.11 draft currently adds *tvalreg registers for additional trap data passing.

[michaeljclark]

There is no major compatibility issue because:

• mtval and mbadaddr have the same CSR number.
• stval and sbadaddr have the same CSR number.

In previous spec versions the tval/badaddr CSRs (which have been renamed in priv v1.10) were only set on address faults in priv v1.9.1, however now they have to be set on all exceptions. It is legal to set them to 0 which is what we do now. We have an outstanding fix for this. See this commit "RISC-V: Clear mtval/stval on exceptions without info" on this branch:

• https://github.com/riscv/riscv-qemu/commits/qemu-2.13-bug-fixes

At some point we should update target/riscv/translate.c to place the instruction bits in tval for illegal instruction exceptions. I have a work-in-progress branch, but it needs debugging:

• https://github.com/michaeljclark/riscv-qemu/tree/wip-mtval-illegal-inst

[michaeljclark]

The minimal compliance for privileged ISA v1.10 is now in master (67185da), which clears mtval/stval on exceptions without address info.

I've raised a new issue to add support for populating mtval/stval with instruction bytes on illegal instruction exceptions #141

I've rebased the WIP branch to master. This branch actually does the rename of badaddr to tval (the CSR number is the same). The rename should probably be split from the commit that adds support for populating tval on illegal instructions: https://github.com/michaeljclark/riscv-qemu/commits/wip-mtval-illegal-inst (this needs testing, as I couldn't get linux to boot with the changes)