Skip to content
This repository has been archived by the owner on Mar 20, 2024. It is now read-only.

Commit

Permalink
vill does not affect instructions that don't depend upon vtype
Browse files Browse the repository at this point in the history
  • Loading branch information
aswaterman committed Feb 13, 2020
1 parent 2352100 commit 4e72221
Showing 1 changed file with 5 additions and 6 deletions.
11 changes: 5 additions & 6 deletions v-spec.adoc
Original file line number Diff line number Diff line change
Expand Up @@ -285,9 +285,11 @@ instruction attempted to write an unsupported value to `vtype`.
NOTE: The `vill` bit is held in bit XLEN-1 of the CSR to support
checking for illegal values with a branch on the sign bit.

If the `vill` bit is set, then any attempt to execute a vector
instruction (other than a vector configuration instruction) will raise
an illegal instruction exception.
If the `vill` bit is set, then any attempt to execute a vector instruction
that depends upon `vtype` will raise an illegal-instruction exception.

This comment has been minimized.

Copy link
@David-Horner

David-Horner Feb 13, 2020

Contributor

excellent. Thanks.

NOTE: `vsetvl{i}` and whole-register loads, stores, and moves do not depend
upon `vtype`.

When the `vill` bit is set, the other XLEN-1 bits in `vtype` shall be
zero.
Expand Down Expand Up @@ -4366,9 +4368,6 @@ NOTE: No elements are moved if `vstart` {ge} VLMAX. The usual property
that no elements are written if `vstart` {ge} `vl` does not apply to
these instructions.

NOTE: Even though these instructions ignore the `vtype` setting,
they still raise an illegal-instruction exception if `vill`=1.

The instruction is encoded as an OPIVI instruction. The number of
vector registers to copy is encoded in the low three bits of the
`simm` field using the same encoding as the `nf` field for memory
Expand Down

0 comments on commit 4e72221

Please sign in to comment.