registers: pmpaddrx: increase addr size to u128 on 64bit platform.

[beezow]

Even though the spec says that the top 10bits of pmpaddrx must be zero, qemu lets you set these to one, allowing a region up to 2^67 in size. We initially removed this feature from #11 during the review process, but I think we should bring it back to allow supporting this qemu configuration. (in particular the SBI sets up the pmps this way...)

[FawazTirmizi]

I am hesitant to have this crate support features that don't conform to the specs (Assuming our interpretation is correct). This sounds like a bug in the SBI implementation and QEMU as opposed to something the crate should be dealing with. If fixing those issues is too cumbersome for now then merging this change is fine and we can revert it later, but otherwise I think we're barking up the wrong tree.

[furquan-rivos]

I am hesitant to have this crate support features that don't conform to the specs (Assuming our interpretation is correct). This sounds like a bug in the SBI implementation and QEMU as opposed to something the crate should be dealing with. If fixing those issues is too cumbersome for now then merging this change is fine and we can revert it later, but otherwise I think we're barking up the wrong tree.

+1. This seems to be a problem with QEMU and SBI implementation. RV Priv spec has bits 63:54 marked as WARL (0). So, these bits can be written as 0 or 1, but should always read back as 0.

Can we add a check in this crate to mask out those bits and not use those? If they are set to 1, probably we can return an error or throw out an error message and mask out those bits and continue decoding.

[beezow]

Fair points, I made this internal PR for qemu.