Update generated files.

librz/analysis/arch/hexagon/hexagon_il.c

@@ -3,7 +3,7 @@
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-21 15:00:15-05:00
+// Date of code generation: 2023-11-21 20:07:05-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:
@@ -268,7 +268,7 @@ static bool set_pkt_il_ops(RZ_INOUT HexPkt *p) {
 	}
 	return true;
 not_impl:
-	RZ_LOG_WARN("Hexagon instruction %" PFMT32d " not implemented.\n", pos->bin.insn->identifier);
+	RZ_LOG_INFO("Hexagon instruction %" PFMT32d " not implemented.\n", pos->bin.insn->identifier);
 	return false;
 }
 
@@ -329,6 +329,9 @@ RZ_IPI RzILOpEffect *hex_get_il_op(const ut32 addr, const bool get_pkt_op) {
 	if (!hic) {
 		return EMPTY();
 	}
+	if (hic->identifier == HEX_INS_INVALID_DECODE) {
+		return NULL;
+	}
 	if (state->just_init || might_has_jumped) {
 		// Assume that the instruction at the address the VM was initialized is the first instruction.
 		// Also make it valid if a jump let to this packet.
@@ -359,7 +362,7 @@ RZ_IPI RzILOpEffect *hex_get_il_op(const ut32 addr, const bool get_pkt_op) {
 	rz_vector_push(p->il_ops, op);
 
 	if (!set_pkt_il_ops(p)) {
-		RZ_LOG_WARN("IL ops at 0x%" PFMT32x " contain not implemented instructions.\n", addr);
+		RZ_LOG_INFO("IL ops at 0x%" PFMT32x " contain not implemented instructions.\n", addr);
 		return NULL;
 	}
 
@@ -564,17 +567,26 @@ RZ_IPI RZ_OWN RzILOpEffect *hex_write_reg(RZ_BORROW HexInsnPktBundle *bundle, co
 	case HEX_REG_CLASS_DOUBLE_REGS:
 	case HEX_REG_CLASS_GENERAL_DOUBLE_LOW8_REGS:
 		high_name = hex_get_reg_in_class(HEX_REG_CLASS_INT_REGS, reg_num + 1, false, true, true);
+		if (!high_name) {
+			return NULL;
+		}
 		high_val = SHIFTR0(DUP(val), U8(HEX_GPR_WIDTH));
 		// fallthrough
 	case HEX_REG_CLASS_INT_REGS:
 	case HEX_REG_CLASS_INT_REGS_LOW8:
 	case HEX_REG_CLASS_GENERAL_SUB_REGS:
 		low_name = hex_get_reg_in_class(HEX_REG_CLASS_INT_REGS, reg_num, false, true, true);
+		if (!low_name) {
+			return NULL;
+		}
 		low_val = CAST(HEX_GPR_WIDTH, IL_FALSE, val);
 		break;
 	case HEX_REG_CLASS_CTR_REGS64:
 		if (hex_ctr_immut_masks[reg_num + 1] != HEX_IMMUTABLE_REG) {
 			high_name = hex_get_reg_in_class(HEX_REG_CLASS_CTR_REGS, reg_num + 1, false, true, true);
+			if (!high_name) {
+				return NULL;
+			}
 			high_val = SHIFTR0(DUP(val), U8(HEX_GPR_WIDTH));
 			if (hex_ctr_immut_masks[reg_num + 1] != 0) {
 				high_val = get_masked_reg_val(VARG(high_name), CAST(HEX_GPR_WIDTH, IL_FALSE, high_val), hex_ctr_immut_masks[reg_num + 1]);
@@ -585,6 +597,9 @@ RZ_IPI RZ_OWN RzILOpEffect *hex_write_reg(RZ_BORROW HexInsnPktBundle *bundle, co
 	case HEX_REG_CLASS_CTR_REGS:
 		if (hex_ctr_immut_masks[reg_num] != HEX_IMMUTABLE_REG) {
 			low_name = hex_get_reg_in_class(HEX_REG_CLASS_CTR_REGS, reg_num, false, true, true);
+			if (!low_name) {
+				return NULL;
+			}
 			low_val = CAST(HEX_GPR_WIDTH, IL_FALSE, val);
 			if (hex_ctr_immut_masks[reg_num] != 0) {
 				low_val = get_masked_reg_val(VARG(low_name), low_val, hex_ctr_immut_masks[reg_num]);
@@ -606,6 +621,9 @@ RZ_IPI RZ_OWN RzILOpEffect *hex_write_reg(RZ_BORROW HexInsnPktBundle *bundle, co
 		break;
 	case HEX_REG_CLASS_PRED_REGS:
 		low_name = hex_get_reg_in_class(HEX_REG_CLASS_PRED_REGS, reg_num, false, true, true);
+		if (!low_name) {
+			return NULL;
+		}
 		if (other_slot_wrote_to_pred(bundle, reg_num)) {
 			// If the register was written before by another slot, the values get ANDed.
 			low_val = LOGAND(VARG(low_name), val);
@@ -705,6 +723,9 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b
 			tmp_reg = true;
 		}
 		high_name = hex_get_reg_in_class(HEX_REG_CLASS_INT_REGS, reg_num + 1, false, tmp_reg, true);
+		if (!high_name) {
+			return NULL;
+		}
 		high_val = SHIFTL0(CAST(HEX_GPR64_WIDTH, IL_FALSE, VARG(high_name)), U8(HEX_GPR_WIDTH));
 		val_width = HEX_GPR64_WIDTH;
 		// fallthrough
@@ -716,6 +737,9 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b
 			tmp_reg = true;
 		}
 		low_name = hex_get_reg_in_class(HEX_REG_CLASS_INT_REGS, reg_num, false, tmp_reg, true);
+		if (!low_name) {
+			return NULL;
+		}
 		low_val = VARG(low_name);
 		break;
 	case HEX_REG_CLASS_CTR_REGS64:
@@ -724,6 +748,9 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b
 			tmp_reg = true;
 		}
 		high_name = hex_get_reg_in_class(HEX_REG_CLASS_CTR_REGS, reg_num + 1, false, tmp_reg, true);
+		if (!high_name) {
+			return NULL;
+		}
 		if (reg_num + 1 == 9) {
 			// C9 = PC. Does not exist in VM as var
 			high_val = SHIFTL0(CAST(HEX_GPR64_WIDTH, IL_FALSE, U32(pkt->pkt_addr)), U8(HEX_GPR_WIDTH));
@@ -753,6 +780,9 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b
 			break;
 		}
 		low_name = hex_get_reg_in_class(HEX_REG_CLASS_CTR_REGS, reg_num, false, tmp_reg, true);
+		if (!low_name) {
+			return NULL;
+		}
 		if (reg_num == 9) {
 			low_val = U32(pkt->pkt_addr);
 		} else {
@@ -765,6 +795,9 @@ RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, b
 			tmp_reg = true;
 		}
 		low_name = hex_get_reg_in_class(HEX_REG_CLASS_PRED_REGS, reg_num, false, tmp_reg, true);
+		if (!low_name) {
+			return NULL;
+		}
 		return VARG(low_name);
 	}
 	if (read_cond_faulty(low_val, high_val, val_width)) {

librz/analysis/arch/hexagon/hexagon_il.h

@@ -3,13 +3,13 @@
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-21 15:00:15-05:00
+// Date of code generation: 2023-11-21 20:07:05-05:00
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-17 15:27:57-05:00
+// Date of code generation: 2023-11-21 19:58:03-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

librz/analysis/arch/hexagon/hexagon_il_getter_table.h

@@ -3,13 +3,13 @@
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-21 15:00:15-05:00
+// Date of code generation: 2023-11-21 20:07:05-05:00
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-17 15:27:57-05:00
+// Date of code generation: 2023-11-21 19:58:03-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

librz/analysis/arch/hexagon/il_ops/hexagon_il_A2_ops.c

@@ -3,7 +3,7 @@
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-21 15:00:15-05:00
+// Date of code generation: 2023-11-21 20:07:05-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:
@@ -756,7 +756,7 @@ RzILOpEffect *hex_il_op_a2_addpsat(HexInsnPktBundle *bundle) {
 	RzILOpPure *op_AND_17 = LOGAND(VARL("__xor"), VARL("__mask"));
 	RzILOpEffect *branch_44 = BRANCH(NON_ZERO(op_AND_17), seq_then_42, seq_else_43);
 
-	RzILOpEffect *instruction_sequence = SEQN(6, op_ASSIGN_3, op_ASSIGN_7, op_ASSIGN_10, op_ASSIGN_13, op_ASSIGN_16, branch_44);
+	RzILOpEffect *instruction_sequence = SEQN(7, op_ASSIGN_3, op_ASSIGN_7, op_ASSIGN_10, op_ASSIGN_13, op_ASSIGN_16, branch_44, EMPTY());
 	return instruction_sequence;
 }
 
@@ -6279,45 +6279,45 @@ RzILOpEffect *hex_il_op_a2_vcmpwgt(HexInsnPktBundle *bundle) {
 	RzILOpEffect *seq_44 = SEQN(2, op_ASSIGN_2, for_43);
 
 	// j = 0x4;
-	RzILOpEffect *op_ASSIGN_46 = SETL("j", SN(32, 4));
+	RzILOpEffect *op_ASSIGN_47 = SETL("j", SN(32, 4));
 
 	// HYB(++j);
-	RzILOpEffect *op_INC_49 = SETL("j", INC(VARL("j"), 32));
+	RzILOpEffect *op_INC_50 = SETL("j", INC(VARL("j"), 32));
 
 	// h_tmp71 = HYB(++j);
-	RzILOpEffect *op_ASSIGN_hybrid_tmp_51 = SETL("h_tmp71", VARL("j"));
+	RzILOpEffect *op_ASSIGN_hybrid_tmp_52 = SETL("h_tmp71", VARL("j"));
 
 	// seq(h_tmp71 = HYB(++j); HYB(++j));
-	RzILOpEffect *seq_52 = SEQN(2, op_ASSIGN_hybrid_tmp_51, op_INC_49);
+	RzILOpEffect *seq_53 = SEQN(2, op_ASSIGN_hybrid_tmp_52, op_INC_50);
 
 	// Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) | (((((st64) ((st32) ((Rss >> 0x20) & 0xffffffff))) > ((st64) ((st32) ((Rtt >> 0x20) & 0xffffffff)))) ? 0x1 : 0x0) << j)));
-	RzILOpPure *op_LSHIFT_54 = SHIFTL0(UN(64, 1), VARL("j"));
-	RzILOpPure *op_NOT_55 = LOGNOT(op_LSHIFT_54);
-	RzILOpPure *op_AND_58 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_55);
-	RzILOpPure *op_RSHIFT_62 = SHIFTRA(DUP(Rss), SN(32, 0x20));
-	RzILOpPure *op_AND_64 = LOGAND(op_RSHIFT_62, SN(64, 0xffffffff));
-	RzILOpPure *op_RSHIFT_70 = SHIFTRA(DUP(Rtt), SN(32, 0x20));
-	RzILOpPure *op_AND_72 = LOGAND(op_RSHIFT_70, SN(64, 0xffffffff));
-	RzILOpPure *op_GT_75 = SGT(CAST(64, MSB(CAST(32, MSB(op_AND_64), DUP(op_AND_64))), CAST(32, MSB(DUP(op_AND_64)), DUP(op_AND_64))), CAST(64, MSB(CAST(32, MSB(op_AND_72), DUP(op_AND_72))), CAST(32, MSB(DUP(op_AND_72)), DUP(op_AND_72))));
-	RzILOpPure *ite_cast_ut64_76 = ITE(op_GT_75, UN(64, 1), UN(64, 0));
-	RzILOpPure *op_LSHIFT_77 = SHIFTL0(ite_cast_ut64_76, VARL("j"));
-	RzILOpPure *op_OR_78 = LOGOR(op_AND_58, op_LSHIFT_77);
-	RzILOpEffect *op_ASSIGN_80 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_78));
+	RzILOpPure *op_LSHIFT_55 = SHIFTL0(UN(64, 1), VARL("j"));
+	RzILOpPure *op_NOT_56 = LOGNOT(op_LSHIFT_55);
+	RzILOpPure *op_AND_59 = LOGAND(CAST(64, IL_FALSE, CAST(32, MSB(READ_REG(pkt, Pd_op, true)), READ_REG(pkt, Pd_op, true))), op_NOT_56);
+	RzILOpPure *op_RSHIFT_63 = SHIFTRA(DUP(Rss), SN(32, 0x20));
+	RzILOpPure *op_AND_65 = LOGAND(op_RSHIFT_63, SN(64, 0xffffffff));
+	RzILOpPure *op_RSHIFT_71 = SHIFTRA(DUP(Rtt), SN(32, 0x20));
+	RzILOpPure *op_AND_73 = LOGAND(op_RSHIFT_71, SN(64, 0xffffffff));
+	RzILOpPure *op_GT_76 = SGT(CAST(64, MSB(CAST(32, MSB(op_AND_65), DUP(op_AND_65))), CAST(32, MSB(DUP(op_AND_65)), DUP(op_AND_65))), CAST(64, MSB(CAST(32, MSB(op_AND_73), DUP(op_AND_73))), CAST(32, MSB(DUP(op_AND_73)), DUP(op_AND_73))));
+	RzILOpPure *ite_cast_ut64_77 = ITE(op_GT_76, UN(64, 1), UN(64, 0));
+	RzILOpPure *op_LSHIFT_78 = SHIFTL0(ite_cast_ut64_77, VARL("j"));
+	RzILOpPure *op_OR_79 = LOGOR(op_AND_59, op_LSHIFT_78);
+	RzILOpEffect *op_ASSIGN_81 = WRITE_REG(bundle, Pd_op, CAST(8, IL_FALSE, op_OR_79));
 
 	// seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 << j))) ...;
-	RzILOpEffect *seq_82 = SEQN(2, op_ASSIGN_80, EMPTY());
+	RzILOpEffect *seq_83 = SEQN(2, op_ASSIGN_81, EMPTY());
 
 	// seq(seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 <<  ...;
-	RzILOpEffect *seq_83 = SEQN(2, seq_82, seq_52);
+	RzILOpEffect *seq_84 = SEQN(2, seq_83, seq_53);
 
 	// while ((j <= 0x7)) { seq(seq(h_tmp71; Pd = ((st8) ((((ut64) ((st32) Pd)) & (~(0x1 <<  ... };
-	RzILOpPure *op_LE_48 = SLE(VARL("j"), SN(32, 7));
-	RzILOpEffect *for_84 = REPEAT(op_LE_48, seq_83);
+	RzILOpPure *op_LE_49 = SLE(VARL("j"), SN(32, 7));
+	RzILOpEffect *for_85 = REPEAT(op_LE_49, seq_84);
 
 	// seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp71; Pd = ((st8) ( ...;
-	RzILOpEffect *seq_85 = SEQN(2, op_ASSIGN_46, for_84);
+	RzILOpEffect *seq_86 = SEQN(2, op_ASSIGN_47, for_85);
 
-	RzILOpEffect *instruction_sequence = SEQN(2, seq_44, seq_85);
+	RzILOpEffect *instruction_sequence = SEQN(4, seq_44, EMPTY(), seq_86, EMPTY());
 	return instruction_sequence;
 }
 

librz/analysis/arch/hexagon/il_ops/hexagon_il_A4_ops.c

@@ -3,7 +3,7 @@
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-21 15:00:15-05:00
+// Date of code generation: 2023-11-21 20:07:05-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:
@@ -2511,7 +2511,7 @@ RzILOpEffect *hex_il_op_a4_vcmpweqi(HexInsnPktBundle *bundle) {
 	// seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp134; Pd = ((st8)  ...;
 	RzILOpEffect *seq_73 = SEQN(2, op_ASSIGN_41, for_72);
 
-	RzILOpEffect *instruction_sequence = SEQN(5, imm_assign_25, seq_38, EMPTY(), seq_73, EMPTY());
+	RzILOpEffect *instruction_sequence = SEQN(4, imm_assign_25, seq_38, EMPTY(), seq_73);
 	return instruction_sequence;
 }
 
@@ -2603,7 +2603,7 @@ RzILOpEffect *hex_il_op_a4_vcmpwgti(HexInsnPktBundle *bundle) {
 	// seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp136; Pd = ((st8)  ...;
 	RzILOpEffect *seq_73 = SEQN(2, op_ASSIGN_41, for_72);
 
-	RzILOpEffect *instruction_sequence = SEQN(4, imm_assign_25, seq_38, EMPTY(), seq_73);
+	RzILOpEffect *instruction_sequence = SEQN(5, imm_assign_25, seq_38, EMPTY(), seq_73, EMPTY());
 	return instruction_sequence;
 }
 
@@ -2695,7 +2695,7 @@ RzILOpEffect *hex_il_op_a4_vcmpwgtui(HexInsnPktBundle *bundle) {
 	// seq(j = 0x4; while ((j <= 0x7)) { seq(seq(h_tmp138; Pd = ((st8)  ...;
 	RzILOpEffect *seq_72 = SEQN(2, op_ASSIGN_40, for_71);
 
-	RzILOpEffect *instruction_sequence = SEQN(4, imm_assign_25, seq_38, seq_72, EMPTY());
+	RzILOpEffect *instruction_sequence = SEQN(3, imm_assign_25, seq_38, seq_72);
 	return instruction_sequence;
 }
 

librz/analysis/arch/hexagon/il_ops/hexagon_il_A5_ops.c

@@ -3,13 +3,13 @@
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-21 15:00:15-05:00
+// Date of code generation: 2023-11-21 20:07:05-05:00
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-17 15:27:57-05:00
+// Date of code generation: 2023-11-21 19:58:03-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

librz/analysis/arch/hexagon/il_ops/hexagon_il_A6_ops.c

@@ -3,13 +3,13 @@
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-21 15:00:15-05:00
+// Date of code generation: 2023-11-21 20:07:05-05:00
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-17 15:27:57-05:00
+// Date of code generation: 2023-11-21 19:58:03-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

librz/analysis/arch/hexagon/il_ops/hexagon_il_A7_ops.c

@@ -3,13 +3,13 @@
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-21 15:00:15-05:00
+// Date of code generation: 2023-11-21 20:07:05-05:00
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-17 15:27:57-05:00
+// Date of code generation: 2023-11-21 19:58:03-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

librz/analysis/arch/hexagon/il_ops/hexagon_il_C2_ops.c

@@ -3,13 +3,13 @@
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-21 15:00:15-05:00
+// Date of code generation: 2023-11-21 20:07:05-05:00
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-17 15:27:57-05:00
+// Date of code generation: 2023-11-21 19:58:03-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

librz/analysis/arch/hexagon/il_ops/hexagon_il_C4_ops.c

@@ -3,13 +3,13 @@
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-21 15:00:15-05:00
+// Date of code generation: 2023-11-21 20:07:05-05:00
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-17 15:27:57-05:00
+// Date of code generation: 2023-11-21 19:58:03-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

librz/analysis/arch/hexagon/il_ops/hexagon_il_F2_ops.c

@@ -3,13 +3,13 @@
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-21 15:00:15-05:00
+// Date of code generation: 2023-11-21 20:07:05-05:00
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-17 15:27:57-05:00
+// Date of code generation: 2023-11-21 19:58:03-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator:

librz/analysis/arch/hexagon/il_ops/hexagon_il_G4_ops.c

@@ -3,13 +3,13 @@
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-21 15:00:15-05:00
+// Date of code generation: 2023-11-21 20:07:05-05:00
 // SPDX-FileCopyrightText: 2021 Rot127 <unisono@quyllur.org>
 // SPDX-License-Identifier: LGPL-3.0-only
 
 // LLVM commit: b6f51787f6c8e77143f0aef6b58ddc7c55741d5c
 // LLVM commit date: 2023-11-15 07:10:59 -0800 (ISO 8601 format)
-// Date of code generation: 2023-11-17 15:27:57-05:00
+// Date of code generation: 2023-11-21 19:58:03-05:00
 //========================================
 // The following code is generated.
 // Do not edit. Repository of code generator: