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Implemented *.t (BIT Opcode Formats)
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@imbillow
imbillow committed Dec 23, 2023
1 parent d06956f commit 5bf27a6
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Showing 2 changed files with 103 additions and 36 deletions.
112 changes: 76 additions & 36 deletions librz/analysis/arch/tricore/tricore_il.inc
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Original file line number Diff line number Diff line change
Expand Up @@ -1392,17 +1392,60 @@ static RzILOpEffect *e_op_op(
const char *r, RzILOpPure *a, RzILOpPure *b, FUNC_OP2 op1, FUNC_OP2 op2) {
return SETG(r, BITS32_U(VARG(r), 0, 1, BOOL_TO_BV32(op1(NON_ZERO(BITS32(VARG(r), 0, 1)), op2(a, b)))));
}

static RzILOpEffect *e_sh_op(
const char *r, RzILOpPure *a, RzILOpPure *b, FUNC_OP2 op1) {
return SETG(r, LOGOR(SHL0(BITS32(VARG(r), 0, 30), 1), BOOL_TO_BV32(op1(a, b))));
}

static RzILOpEffect *e_op_bit(
RzAsmTriCoreContext *ctx, FUNC_OP2 op) {
return SETG(R(0), BOOL_TO_BV32(op(NON_ZERO(BITS32(VARG(R(1)), I(2), 1)), NON_ZERO(BITS32(VARG(R(3)), I(4), 1)))));
}
static RzILOpEffect *e_op_op_bit(
RzAsmTriCoreContext *ctx, FUNC_OP2 op1, FUNC_OP2 op2) {
return e_op_op(R(0), NON_ZERO(BITS32(VARG(R(1)), I(2), 1)), NON_ZERO(BITS32(VARG(R(3)), I(4), 1)), op1, op2);
}
static RzILOpEffect *e_sh_op_bit(
RzAsmTriCoreContext *ctx, FUNC_OP2 op1) {
return SETG(R(0), LOGOR(SHL0(BITS32(VARG(R(0)), 0, 30), 1), BOOL_TO_BV32(op1(NON_ZERO(BITS32(VARG(R(1)), I(2), 1)), NON_ZERO(BITS32(VARG(R(3)), I(4), 1))))));
}
static RzILOpEffect *e_ins_bit(
RzAsmTriCoreContext *ctx, bool inv) {
unsigned pos1 = I(2);
unsigned pos2 = I(4);
RzILOpPure *b = SHL0(BITS32(VARG(R(3)), pos2, 1), pos1);
b = inv ? LOGNOT(b) : b;
return SETG(R(0),
LOGOR(SHL0(BITS32(VARG(R(0)), pos1 + 1, 32 - pos1 - 1), pos1 + 1),
LOGOR(BITS32(VARG(R(1)), 0, pos1), b)));
}

static RzILOpEffect *e_op2(
const char *r, RzILOpPure *a, RzILOpPure *b, FUNC_OP2 op) {
return SETG(r, op(a, b));
}

static RzILOpPure *f_andn(
RzILOpPure *a, RzILOpPure *b) {
return AND(a, INV(b));
}
static RzILOpPure *f_nor(
RzILOpPure *a, RzILOpPure *b) {
return INV(OR(a, b));
}
static RzILOpPure *f_nand(
RzILOpPure *a, RzILOpPure *b) {
return INV(AND(a, b));
}
static RzILOpPure *f_orn(
RzILOpPure *a, RzILOpPure *b) {
return OR(a, INV(b));
}
static RzILOpPure *f_xnor(
RzILOpPure *a, RzILOpPure *b) {
return INV(XOR(a, b));
}

static RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *a) {
ctx->word = rz_read_le32(ctx->insn->bytes);
switch (ctx->insn->id) {
Expand Down Expand Up @@ -1493,14 +1536,6 @@ static RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
case TRICORE_INS_CADDN:
case TRICORE_INS_CADD_A:
case TRICORE_INS_CADD: return lift_cadd(ctx);
case TRICORE_INS_ANDN_T:
case TRICORE_INS_AND_ANDN_T:
case TRICORE_INS_AND_AND_T:
case TRICORE_INS_AND_NOR_T:
case TRICORE_INS_AND_OR_T:
case TRICORE_INS_AND_T: {
break;
}
case TRICORE_INS_BISR:
case TRICORE_INS_SYSCALL:
case TRICORE_INS_DISABLE:
Expand Down Expand Up @@ -1542,15 +1577,10 @@ static RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
case TRICORE_INS_NOP: {
break;
}
case TRICORE_INS_NOR_T: {
break;
}
case TRICORE_INS_DEXTR:
case TRICORE_INS_EXTR_U:
case TRICORE_INS_EXTR:
case TRICORE_INS_INSERT:
case TRICORE_INS_INSN_T:
case TRICORE_INS_INS_T: {
case TRICORE_INS_INSERT: {
break;
}
case TRICORE_INS_DIFSC_A: {
Expand Down Expand Up @@ -1974,18 +2004,37 @@ static RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
case TRICORE_INS_MUL: {
break;
}
case TRICORE_INS_NAND_T: {
break;
}
case TRICORE_INS_AND_AND_T: return e_op_op_bit(ctx, rz_il_op_new_bool_and, rz_il_op_new_bool_and);
case TRICORE_INS_AND_ANDN_T: return e_op_op_bit(ctx, rz_il_op_new_bool_and, f_andn);
case TRICORE_INS_AND_NOR_T: return e_op_op_bit(ctx, rz_il_op_new_bool_and, f_nor);
case TRICORE_INS_AND_OR_T: return e_op_op_bit(ctx, rz_il_op_new_bool_and, rz_il_op_new_bool_or);

case TRICORE_INS_OR_AND_T: return e_op_op_bit(ctx, rz_il_op_new_bool_or, rz_il_op_new_bool_and);
case TRICORE_INS_OR_ANDN_T: return e_op_op_bit(ctx, rz_il_op_new_bool_or, f_andn);
case TRICORE_INS_OR_NOR_T: return e_op_op_bit(ctx, rz_il_op_new_bool_or, f_nor);
case TRICORE_INS_OR_OR_T: return e_op_op_bit(ctx, rz_il_op_new_bool_or, rz_il_op_new_bool_or);

case TRICORE_INS_SH_AND_T: return e_sh_op_bit(ctx, rz_il_op_new_bool_and);
case TRICORE_INS_SH_ANDN_T: return e_sh_op_bit(ctx, f_andn);
case TRICORE_INS_SH_NAND_T: return e_sh_op_bit(ctx, f_nand);
case TRICORE_INS_SH_NOR_T: return e_sh_op_bit(ctx, f_nor);
case TRICORE_INS_SH_ORN_T: return e_sh_op_bit(ctx, f_orn);
case TRICORE_INS_SH_OR_T: return e_sh_op_bit(ctx, rz_il_op_new_bool_or);
case TRICORE_INS_SH_XNOR_T: return e_sh_op_bit(ctx, f_xnor);
case TRICORE_INS_SH_XOR_T: return e_sh_op_bit(ctx, rz_il_op_new_bool_xor);

case TRICORE_INS_AND_T: return e_op_bit(ctx, rz_il_op_new_bool_and);
case TRICORE_INS_OR_T: return e_op_bit(ctx, rz_il_op_new_bool_or);
case TRICORE_INS_ANDN_T: return e_op_bit(ctx, f_andn);
case TRICORE_INS_NOR_T: return e_op_bit(ctx, f_nor);
case TRICORE_INS_NAND_T: return e_op_bit(ctx, f_nand);
case TRICORE_INS_ORN_T: return e_op_bit(ctx, f_orn);
case TRICORE_INS_XNOR_T: return e_op_bit(ctx, f_xnor);
case TRICORE_INS_XOR_T: return e_op_bit(ctx, rz_il_op_new_bool_xor);

case TRICORE_INS_INS_T: return e_ins_bit(ctx, false);
case TRICORE_INS_INSN_T: return e_ins_bit(ctx, true);

case TRICORE_INS_ORN_T:
case TRICORE_INS_OR_ANDN_T:
case TRICORE_INS_OR_AND_T:
case TRICORE_INS_OR_NOR_T:
case TRICORE_INS_OR_OR_T:
case TRICORE_INS_OR_T: {
break;
}
case TRICORE_INS_PARITY:
case TRICORE_INS_POPCNT_W: {
break;
Expand All @@ -2009,16 +2058,9 @@ static RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
case TRICORE_INS_SHA_B:
case TRICORE_INS_SHA_H:
case TRICORE_INS_SHA:
case TRICORE_INS_SH_ANDN_T:
case TRICORE_INS_SH_AND_T:

case TRICORE_INS_SH_B:
case TRICORE_INS_SH_H:
case TRICORE_INS_SH_NAND_T:
case TRICORE_INS_SH_NOR_T:
case TRICORE_INS_SH_ORN_T:
case TRICORE_INS_SH_OR_T:
case TRICORE_INS_SH_XNOR_T:
case TRICORE_INS_SH_XOR_T:
case TRICORE_INS_SH: {
break;
}
Expand Down Expand Up @@ -2101,8 +2143,6 @@ static RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
case TRICORE_INS_TRAPV: {
break;
}
case TRICORE_INS_XNOR_T:
case TRICORE_INS_XOR_T: break;
case TRICORE_INS_AND:
case TRICORE_INS_ANDN:
case TRICORE_INS_NAND:
Expand Down
27 changes: 27 additions & 0 deletions test/db/asm/tricore
View file
Original file line number Diff line number Diff line change
Expand Up @@ -248,3 +248,30 @@ d "xnor d0, d0, #0" 8f00a001 0x0 (set d0 (~ (^ (var d0) (bv 32 0x0))))
d "xor d0, d0" c600 0x0 (set d0 (^ (var d0) (var d0)))
d "xor d0, d0, d0" 0f00c000 0x0 (set d0 (^ (var d0) (var d0)))
d "xor d0, d0, #0" 8f008001 0x0 (set d0 (^ (var d0) (bv 32 0x0)))
d "and.and.t d0, d0, #0, d0, #0" 47000000 0x0 (set d0 (| (& (var d0) (bv 32 0xfffffffe)) (<< (& (ite (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x0) false)))
d "and.andn.t d0, d0, #0, d0, #0" 47006000 0x0 (set d0 (| (& (var d0) (bv 32 0xfffffffe)) (<< (& (ite (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1))))))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x0) false)))
d "and.nor.t d0, d0, #0, d0, #0" 47004000 0x0 (set d0 (| (& (var d0) (bv 32 0xfffffffe)) (<< (& (ite (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1))))))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x0) false)))
d "and.or.t d0, d0, #0, d0, #0" 47002000 0x0 (set d0 (| (& (var d0) (bv 32 0xfffffffe)) (<< (& (ite (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x0) false)))
d "and.t d0, d0, #0, d0, #0" 87000000 0x0 (set d0 (ite (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1))))) (bv 32 0x1) (bv 32 0x0)))
d "andn.t d0, d0, #0, d0, #0" 87006000 0x0 (set d0 (ite (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0)))
d "nand.t d0, d0, #0, d0, #0" 07000000 0x0 (set d0 (ite (! (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0)))
d "nor.t d0, d0, #0, d0, #0" 87004000 0x0 (set d0 (ite (! (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0)))
d "or.and.t d0, d0, #0, d0, #0" c7000000 0x0 (set d0 (| (& (var d0) (bv 32 0xfffffffe)) (<< (& (ite (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x0) false)))
d "or.andn.t d0, d0, #0, d0, #0" c7006000 0x0 (set d0 (| (& (var d0) (bv 32 0xfffffffe)) (<< (& (ite (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1))))))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x0) false)))
d "or.nor.t d0, d0, #0, d0, #0" c7004000 0x0 (set d0 (| (& (var d0) (bv 32 0xfffffffe)) (<< (& (ite (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1))))))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x0) false)))
d "or.or.t d0, d0, #0, d0, #0" c7002000 0x0 (set d0 (| (& (var d0) (bv 32 0xfffffffe)) (<< (& (ite (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x0) false)))
d "or.t d0, d0, #0, d0, #0" 87002000 0x0 (set d0 (ite (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1))))) (bv 32 0x1) (bv 32 0x0)))
d "orn.t d0, d0, #0, d0, #0" 07002000 0x0 (set d0 (ite (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0)))
d "orn.t d0, d0, #0, d0, #0" 07002000 0x0 (set d0 (ite (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0)))
d "sh.and.t d0, d0, #0, d0, #0" 27000000 0x0 (set d0 (| (<< (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x3fffffff)) (bv 32 0x1) false) (ite (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1))))) (bv 32 0x1) (bv 32 0x0))))
d "sh.andn.t d0, d0, #0, d0, #0" 27006000 0x0 (set d0 (| (<< (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x3fffffff)) (bv 32 0x1) false) (ite (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0))))
d "sh.nand.t d0, d0, #0, d0, #0" a7000000 0x0 (set d0 (| (<< (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x3fffffff)) (bv 32 0x1) false) (ite (! (&& (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0))))
d "sh.nor.t d0, d0, #0, d0, #0" 27004000 0x0 (set d0 (| (<< (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x3fffffff)) (bv 32 0x1) false) (ite (! (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0))))
d "sh.or.t d0, d0, #0, d0, #0" 27002000 0x0 (set d0 (| (<< (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x3fffffff)) (bv 32 0x1) false) (ite (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1))))) (bv 32 0x1) (bv 32 0x0))))
d "sh.orn.t d0, d0, #0, d0, #0" a7002000 0x0 (set d0 (| (<< (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x3fffffff)) (bv 32 0x1) false) (ite (|| (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0))))
d "sh.xnor.t d0, d0, #0, d0, #0" a7004000 0x0 (set d0 (| (<< (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x3fffffff)) (bv 32 0x1) false) (ite (! (^^ (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0))))
d "sh.xor.t d0, d0, #0, d0, #0" a7006000 0x0 (set d0 (| (<< (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x3fffffff)) (bv 32 0x1) false) (ite (^^ (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1))))) (bv 32 0x1) (bv 32 0x0))))
d "xnor.t d0, d0, #0, d0, #0" 07004000 0x0 (set d0 (ite (! (^^ (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))))) (bv 32 0x1) (bv 32 0x0)))
d "xor.t d0, d0, #0, d0, #0" 07006000 0x0 (set d0 (ite (^^ (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1))))) (bv 32 0x1) (bv 32 0x0)))
d "ins.t d0, d0, #0, d0, #0" 67000000 0x0 (set d0 (| (<< (& (>> (var d0) (bv 32 0x1) false) (bv 32 0x7fffffff)) (bv 32 0x1) false) (| (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x0)) (<< (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0) false))))
d "insn.t d0, d0, #0, d0, #0" 67002000 0x0 (set d0 (| (<< (& (>> (var d0) (bv 32 0x1) false) (bv 32 0x7fffffff)) (bv 32 0x1) false) (| (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x0)) (~ (<< (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0) false)))))

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