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Make AArch64/ARM analysis and asm plugins Capstone v6 compatible. (#4011
) This commit refactors the AArch64 and partially the ARM plugin to make it Capstone v6 compatible. Due to the big API changes in Capstone v6 several changes had to be made. Because we need to be compatible to Capstone v4 and v5 many include guards are added as well. Overview of changes done: **ARM** - Instruction alias were introduced. This leads to different decoding and analysis paths taken for certain instructions. Some alias have their IL code generated like the real instruction now (no special handling needed anymore). This change is responsible for many changes you'll encounter. - The operand details of each instruction are now always the one of the real instruction. Also for alias. For example, if "MOV <Wd>, #<imm>" is an alias for `ORR <Wd>, WZR, #<imm>`, the details by CS hold all three operands of "ORR". Before, they held only the two of "MOV". - Several bugs in variable and argument generation were fixed. Especially the default variable width for ARM Thumb was changed to 32bit instead of the 16bit. **AArch64/ARM64** The changes listed above for ARM, also apply to AArch64. Additionally: - Capstone v6 changed the name ARM64 now everywhere to AArch64. To be compatible with Capstone v4/v5 AArch64 names must be wrapped into macros which resolve the name, depending on the CS version used. - Capstone v6 is now more consistent with register real and alias names. From now on we use the register alias by default. **List squashed commit messages:** [AArch64 CS v6 BEGIN] Change subproject config to use cs-auto-sync-aarch64 branch Replace ARM64 with version sensitive macros. Exclude alias if CS version >= 6 Update access to writeback member Exclude instr alias from inclusion Update memory operand printing to json. Enable real instr. detail only for AArch64 Set correct arch name in meson.build for CS Fix U/SBFM instructions and their alias. Mark parameters with RZ_OUt/BORROW Optimize register extension to skip some, if the width already matches. Adapt width and lsb of U/SBFM alias instructions (ImmR and ImmS are from U/SBFM). Fix tests correct semantic buy bad syntax Pass alias MOV instructions to mov() Handle CSET and CSETM alias Fix lsl, lsr and asr by handling them as alias. Fix mov alias. Handle TST alias Fix CNEG, CINV alias Fix bfi and bfxil alias. Fix sign extensions. Fix compare instructions. Fix NEG, NGC, NGCS, NEGS, MVN Fix CINC Fix multiply instructions. Fix ROR Run clang-format Handle CMP for ESIL Handle new position of memory disponents of post index operands. Fix post-index operations. Add missing writeback checks for Post and preindex Handle UBFM and SBFM alias Handl BFM alias Handle CMP, CSET and CINC alias Update meson file of for cs-aarch64 branch Fix asm tests. Use reg alias now. Fix condition confusion and incorrect operand usage. Fix plf test. Run clang-format Use register alias in tests Add support for fp and lr reg alias assembly. Use reg alias in test Rename cond tranlate functions r2 -> rz Fix condition check which assume 0 == invalid. Fix issues intruduced by rebase Set CS commit to current next branch. Rename ARM64 -> AArch64 Add missing source file to meson.build Remove DisassemblerExtension.c file for CS v5 Update to newest capstone next branch Bump up CS version REVERT ME: Get Capstone v4/v5 via git clone until new tars are released. Wrap setting of CS_DETAIL_REAL into CS version check Add maybe-unitialized to Capstone C args. Fix CS pre v6 build by adding guards. Use reg alias now printed by default by CS. Bump CS version to most recent next. Fix build errors due to stircter alias handling in ARM. Fix RzIL tests introduced by alias introduction to ARM. Fix ESIL bugs introduced with ARM alias introduction. - stackptr hasn't been set for POP and PUSH Add support again for Thumb1 pop/push Handle PUSHW and POPW alias Update test case Add more POP and PUSH alias and enrich detail for other versions of them. Fix incorrect mem access width guesses for ARM thumb. Set POP return info if it writes to PC Fix tests about default var size and POP mem write direction. Bump CS version to newest next. Fix incorrect tests. - TriCore: Functions were in ro section. - Default arg width in ARM thumb is 32bit. Revert check for a set stackptr. stackptr is used in different ways: 1. Safes the offset from the stack frame base. 2. Is interpreted as somthing else for x86 and I cannot find out what, in a reasonably time. Hence we cannot use it here consistently. Remove check for non existing ARM_GRP_RET in CSv5 Fix incorrect stack offsets of variables. 'push <reg-list>' instructions for which the second register was the FP, reset the stackptr variable to 0. This led to wrong bp offsets in the variable names. In this case it was +0xc. Bump CS version. Add copy of meta-programming macros for capstone-sys build. Update capstone-next.wrap Use bracket-less met-programming macro to fix Windows build warnings. Update wrap files for Capstone with branch names Add new meta-programming macro Add workaround for MSVC pre-processor bug.
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