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[RzArch] Progress tracker #4334

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4 of 73 tasks
Rot127 opened this issue Mar 5, 2024 · 0 comments
Open
4 of 73 tasks

[RzArch] Progress tracker #4334

Rot127 opened this issue Mar 5, 2024 · 0 comments
Labels
blocker rz-asm RzAnalysis RzArch RzAsm-Disassembler RzParse
Milestone
0.8.0

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@Rot127
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Rot127 commented Mar 5, 2024 •
edited by XVilka
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Tracking issue for RzArch

Refactor old plugin

Extensions and new RzArch plugin

  • Add new RzArch plugin (see: RzArch #2557)
  • Add compatibility functions (since we need to support asm/analysis/arch for a while all at once):
    • Wrap old RzAnalysis and RzAsm API functions into some new functions. They should check if the plugin is a RzArch plugin and call the new API if yes.
    • If RzArch returns different objects/data/values whatever, translate them for core
  • Refactor each archs asm and analysis plugin into the new RzArch plugin
    • 6502
    • 8051
    • amd29k
    • arc
    • arm
    • avr
    • cil
    • cr16
    • cris
    • dalvik
    • dcpu16
    • ebc
    • gb
    • h8300
    • hexagon
    • hppa
    • i4004
    • i8080
    • include
    • java
    • lanai
    • lh5801
    • lm32
    • luac
    • mcore
    • mcs96
    • mips
    • msp430
    • nios
    • or1k
    • pic
    • ppc
    • propeller
    • pyc
    • riscv
    • rl78
    • rsp
    • rx
    • sh
    • snes
    • sparc
    • spc700
    • tms320
    • tricore
    • v810
    • v850
    • vax
    • wasm
    • xap
    • xtensa
    • z80
  • Refactor bindings generation (rz-bindgen)
  • Refactor external plugins
    • rz-ghidra
    • jsdec
    • rizin-extras
    • Cutter
  • Move certain APIs to own plugins:
  • Remove compatibility code and make core use only the new RzArch API.
  • Update code documentation and book
  • Others
    • Address

      rizin/librz/arch/isa/hexagon/hexagon_il.c

      Lines 243 to 247 in fb6efca

      // This function is a lot of unnecessary overhead so:
      // TODO The assignment of IL instructions to their actual instructions should be done in the instruction template.
      // But with the current separation between Asm and Analysis plugins this is not possible.
      // Because Asm is not allowed to depend on Analysis and the RZIL code.
      // This should be fixed ASAP after RzArch has been introduced.
@Rot127 Rot127 added this to the 0.8.0 milestone Mar 5, 2024
@XVilka XVilka added the blocker label Mar 5, 2024
@Rot127 Rot127 mentioned this issue Mar 21, 2024
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20 tasks
@XVilka XVilka mentioned this issue Apr 7, 2024
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@XVilka XVilka mentioned this issue May 7, 2024
Open
@XVilka XVilka mentioned this issue Oct 1, 2024
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5 tasks
Rot127 added a commit to Rot127/rizin that referenced this issue Oct 6, 2024
@Rot127
Mark M68k tesst broken.
d40ba92 
This test is broken. The reason is that Rizin can't distinguish
CPU models. Each M68k model has a different address mask (32-24 bits).
It defaults to one which has only 24bits.
Hence, the subi.l instruction decodes to
'subi.l 0x15b119, d0' instead of 'subi.l 0x8015b119, d0'
Should be fixable with RzArch (if anyone is still intereses).
See: rizinorg#4334
Rot127 added a commit to Rot127/rizin that referenced this issue Oct 23, 2024
@Rot127
Mark M68k tesst broken.
333f851 
This test is broken. The reason is that Rizin can't distinguish
CPU models. Each M68k model has a different address mask (32-24 bits).
It defaults to one which has only 24bits.
Hence, the subi.l instruction decodes to
'subi.l 0x15b119, d0' instead of 'subi.l 0x8015b119, d0'
Should be fixable with RzArch (if anyone is still intereses).
See: rizinorg#4334
Rot127 added a commit to Rot127/rizin that referenced this issue Oct 24, 2024
@Rot127
Mark M68k tesst broken.
b7eca1f 
This test is broken. The reason is that Rizin can't distinguish
CPU models. Each M68k model has a different address mask (32-24 bits).
It defaults to one which has only 24bits.
Hence, the subi.l instruction decodes to
'subi.l 0x15b119, d0' instead of 'subi.l 0x8015b119, d0'
Should be fixable with RzArch (if anyone is still intereses).
See: rizinorg#4334
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