-
Notifications
You must be signed in to change notification settings - Fork 0
Issues: rlee287/hardware-bus-infrastructure
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Author
Label
Projects
Milestones
Assignee
Sort
Issues list
Code Review Backlog Tracker
help wanted
Extra attention is needed
#12
opened Feb 12, 2021 by
rlee287
1 task
Add brief explanation of how to use properties and verify cores with SymbiYosys
Example Cores
Formal Property Set
#11
opened Feb 12, 2021 by
rlee287
Set up CI infrastructure for testing property sets with example cores
Example Cores
Formal Property Set
#10
opened Jan 4, 2021 by
rlee287
Add appropriate output signals to AXI-Stream formal properties
AXI-Stream
Formal Property Set
#9
opened Jan 3, 2021 by
rlee287
Add multiclock support to AXI-Stream properties
AXI-Stream
Formal Property Set
#8
opened Jan 3, 2021 by
rlee287
Create AXI-Stream processing core properties
AXI-Stream
Formal Property Set
#6
opened Dec 27, 2020 by
rlee287
Add support for asynchronous resets to AXI-Stream properties
AXI-Stream
Formal Property Set
#4
opened Dec 14, 2020 by
rlee287
Create AXI-Stream Formal Property Set
AXI-Stream
Formal Property Set
#1
opened Dec 5, 2020 by
rlee287
ProTip!
Exclude everything labeled
bug
with -label:bug.