[128-bit] FPGA Implementation of a Asynchronous Quasi-Random Number Generator Using Linear-feedback Shift Registers and Mousetrap Logic
by: Rodrigo N. Wuerdig, Marcos L. L. Sartori, and Ney L. V. Calazans
Goals
- Increase Entropy Through Time Displacement
- Fully Digital High Variability Number Generator
Fig. I - Mousetrap Asynchronous QRNG Architecture
Test-Bench
This circuit was prototyped on a Nexys board equipped with a Xilinx XC3S200 Spartan-3 FPGA.
More info here: https://ieeexplore.ieee.org/abstract/document/8667561/
R. N. Wuerdig, M. L. L. Sartori and N. L. V. Calazans, "Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations," 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), Armenia, Colombia, 2019, pp. 137-140, doi: 10.1109/LASCAS.2019.8667561.