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New Rule: Forbid unpacked array declarations
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ronitnallagatla committed Feb 15, 2024
1 parent 0530ce6 commit b96b20b
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8 changes: 8 additions & 0 deletions md/syntaxrules-explanation-unpacked_array.md
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This rule forbids unpacked array declarations.

Unpacked arrays are not guaranteed to be represented as contiguous memory, and can cause issues with synthesis tools, especially with how multidimensional arrays are synthesized. For example, a synthesis tool might synthesize out unused memory locations of an unpacked array which is not the intended behavior.

Additionally, packed arrays allow the user to intuitively index and slice the array and apply bitwise operations.

The most relevant clauses of IEEE1800-2017 are:
- 7.4 Packed and unpacked arrays
38 changes: 38 additions & 0 deletions src/syntaxrules/unpacked_array.rs
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use crate::config::ConfigOption;
use crate::linter::{SyntaxRule, SyntaxRuleResult};
use sv_parser::{NodeEvent, RefNode, SyntaxTree};

#[derive(Default)]
pub struct UnpackedArray;

impl SyntaxRule for UnpackedArray {
fn check(
&mut self,
_syntax_tree: &SyntaxTree,
event: &NodeEvent,
_option: &ConfigOption,
) -> SyntaxRuleResult {
let node = match event {
NodeEvent::Enter(x) => x,
NodeEvent::Leave(_) => {
return SyntaxRuleResult::Pass;
}
};

match node {
RefNode::UnpackedDimension(_) => SyntaxRuleResult::Fail,
_ => SyntaxRuleResult::Pass,
}
}
fn name(&self) -> String {
String::from("unpacked_array")
}

fn hint(&self, _option: &ConfigOption) -> String {
String::from("Avoid using unpacked arrays in variable declarations.")
}

fn reason(&self) -> String {
String::from("Unpacked arrays can lead to issues during synthesis.")
}
}
11 changes: 11 additions & 0 deletions testcases/syntaxrules/fail/unpacked_array.sv
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module M;

logic a [7:0];

endmodule;
////////////////////////////////////////////////////////////////////////////////
module M;

logic [31:0] b [0:7];

endmodule;
11 changes: 11 additions & 0 deletions testcases/syntaxrules/pass/unpacked_array.sv
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module M;

logic [31:0] a;

endmodule
////////////////////////////////////////////////////////////////////////////////
module M;

logic [7:0][3:0] b;

endmodule

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