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MANUAL.md

@@ -5337,7 +5337,7 @@ Avoid using unpacked dimensions in declarations.
 
 ### Reason
 
-Unpacked arrays can lead to issues during synthesis.
+Unpacked arrays are not guaranteed to be contiguous and can lead to synthesis issues.
 
 ### Pass Example (1 of 2)
 ```systemverilog
@@ -5357,7 +5357,7 @@ logic [7:0][3:0] b;
 endmodule
 ```
 
-### Fail Example (1 of 7)
+### Fail Example (1 of 2)
 ```systemverilog
 module M;
 
@@ -5366,7 +5366,7 @@ logic a [7:0];
 endmodule;
 ```
 
-### Fail Example (2 of 7)
+### Fail Example (2 of 2)
 ```systemverilog
 module M;
 
@@ -5375,50 +5375,6 @@ logic [31:0] b [0:7];
 endmodule;
 ```
 
-### Fail Example (3 of 7)
-```systemverilog
-module M;
-
-localparam bit [7:0] ARRAY [0:3];
-
-endmodule
-```
-
-### Fail Example (4 of 7)
-```systemverilog
-module M (
-  input logic [7:0] a_in [0:5]
-);
-endmodule
-```
-
-### Fail Example (5 of 7)
-```systemverilog
-module M;
-
-parameter [3:0] ARRAY [0:1];
-
-endmodule
-```
-
-### Fail Example (6 of 7)
-```systemverilog
-module M;
-
-wire [3:0] c [0:1];
-
-endmodule
-```
-
-### Fail Example (7 of 7)
-```systemverilog
-module M;
-
-var [3:0] d [0:1];
-
-endmodule
-```
-
 ### Explanation
 
 This rule forbids unpacked array declarations.