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jannic committed Feb 27, 2024
1 parent 9514f49 commit 0f99370
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Showing 399 changed files with 1,079 additions and 4,304 deletions.
2 changes: 1 addition & 1 deletion src/adc.rs
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
#[doc = r"Register block"]
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
cs: CS,
result: RESULT,
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11 changes: 1 addition & 10 deletions src/adc/cs.rs
Original file line number Diff line number Diff line change
Expand Up @@ -142,16 +142,6 @@ impl W {
pub fn rrobin(&mut self) -> RROBIN_W<CS_SPEC> {
RROBIN_W::new(self, 16)
}
#[doc = r" Writes raw bits to the register."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = "ADC Control and Status
Expand All @@ -164,6 +154,7 @@ impl crate::RegisterSpec for CS_SPEC {
impl crate::Readable for CS_SPEC {}
#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"]
impl crate::Writable for CS_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0400;
}
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11 changes: 1 addition & 10 deletions src/adc/div.rs
Original file line number Diff line number Diff line change
Expand Up @@ -35,16 +35,6 @@ impl W {
pub fn int(&mut self) -> INT_W<DIV_SPEC> {
INT_W::new(self, 8)
}
#[doc = r" Writes raw bits to the register."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions
at regular intervals rather than back-to-back.
Expand All @@ -60,6 +50,7 @@ impl crate::RegisterSpec for DIV_SPEC {
impl crate::Readable for DIV_SPEC {}
#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"]
impl crate::Writable for DIV_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
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11 changes: 1 addition & 10 deletions src/adc/fcs.rs
Original file line number Diff line number Diff line change
Expand Up @@ -131,16 +131,6 @@ impl W {
pub fn thresh(&mut self) -> THRESH_W<FCS_SPEC> {
THRESH_W::new(self, 24)
}
#[doc = r" Writes raw bits to the register."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = "FIFO control and status
Expand All @@ -153,6 +143,7 @@ impl crate::RegisterSpec for FCS_SPEC {
impl crate::Readable for FCS_SPEC {}
#[doc = "`write(|w| ..)` method takes [`fcs::W`](W) writer structure"]
impl crate::Writable for FCS_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x0c00;
}
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11 changes: 1 addition & 10 deletions src/adc/inte.rs
Original file line number Diff line number Diff line change
Expand Up @@ -24,16 +24,6 @@ impl W {
pub fn fifo(&mut self) -> FIFO_W<INTE_SPEC> {
FIFO_W::new(self, 0)
}
#[doc = r" Writes raw bits to the register."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = "Interrupt Enable
Expand All @@ -46,6 +36,7 @@ impl crate::RegisterSpec for INTE_SPEC {
impl crate::Readable for INTE_SPEC {}
#[doc = "`write(|w| ..)` method takes [`inte::W`](W) writer structure"]
impl crate::Writable for INTE_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
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11 changes: 1 addition & 10 deletions src/adc/intf.rs
Original file line number Diff line number Diff line change
Expand Up @@ -24,16 +24,6 @@ impl W {
pub fn fifo(&mut self) -> FIFO_W<INTF_SPEC> {
FIFO_W::new(self, 0)
}
#[doc = r" Writes raw bits to the register."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = "Interrupt Force
Expand All @@ -46,6 +36,7 @@ impl crate::RegisterSpec for INTF_SPEC {
impl crate::Readable for INTF_SPEC {}
#[doc = "`write(|w| ..)` method takes [`intf::W`](W) writer structure"]
impl crate::Writable for INTF_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
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2 changes: 1 addition & 1 deletion src/busctrl.rs
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
#[doc = r"Register block"]
#[repr(C)]
#[doc = "Register block"]
pub struct RegisterBlock {
bus_priority: BUS_PRIORITY,
bus_priority_ack: BUS_PRIORITY_ACK,
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11 changes: 1 addition & 10 deletions src/busctrl/bus_priority.rs
Original file line number Diff line number Diff line change
Expand Up @@ -65,16 +65,6 @@ impl W {
pub fn dma_w(&mut self) -> DMA_W_W<BUS_PRIORITY_SPEC> {
DMA_W_W::new(self, 12)
}
#[doc = r" Writes raw bits to the register."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = "Set the priority of each master for bus arbitration.
Expand All @@ -87,6 +77,7 @@ impl crate::RegisterSpec for BUS_PRIORITY_SPEC {
impl crate::Readable for BUS_PRIORITY_SPEC {}
#[doc = "`write(|w| ..)` method takes [`bus_priority::W`](W) writer structure"]
impl crate::Writable for BUS_PRIORITY_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
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11 changes: 1 addition & 10 deletions src/busctrl/perfctr0.rs
Original file line number Diff line number Diff line change
Expand Up @@ -28,16 +28,6 @@ impl W {
pub fn perfctr0(&mut self) -> PERFCTR0_W<PERFCTR0_SPEC> {
PERFCTR0_W::new(self, 0)
}
#[doc = r" Writes raw bits to the register."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = "Bus fabric performance counter 0
Expand All @@ -50,6 +40,7 @@ impl crate::RegisterSpec for PERFCTR0_SPEC {
impl crate::Readable for PERFCTR0_SPEC {}
#[doc = "`write(|w| ..)` method takes [`perfctr0::W`](W) writer structure"]
impl crate::Writable for PERFCTR0_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff;
}
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11 changes: 1 addition & 10 deletions src/busctrl/perfctr1.rs
Original file line number Diff line number Diff line change
Expand Up @@ -28,16 +28,6 @@ impl W {
pub fn perfctr1(&mut self) -> PERFCTR1_W<PERFCTR1_SPEC> {
PERFCTR1_W::new(self, 0)
}
#[doc = r" Writes raw bits to the register."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = "Bus fabric performance counter 1
Expand All @@ -50,6 +40,7 @@ impl crate::RegisterSpec for PERFCTR1_SPEC {
impl crate::Readable for PERFCTR1_SPEC {}
#[doc = "`write(|w| ..)` method takes [`perfctr1::W`](W) writer structure"]
impl crate::Writable for PERFCTR1_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff;
}
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11 changes: 1 addition & 10 deletions src/busctrl/perfctr2.rs
Original file line number Diff line number Diff line change
Expand Up @@ -28,16 +28,6 @@ impl W {
pub fn perfctr2(&mut self) -> PERFCTR2_W<PERFCTR2_SPEC> {
PERFCTR2_W::new(self, 0)
}
#[doc = r" Writes raw bits to the register."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = "Bus fabric performance counter 2
Expand All @@ -50,6 +40,7 @@ impl crate::RegisterSpec for PERFCTR2_SPEC {
impl crate::Readable for PERFCTR2_SPEC {}
#[doc = "`write(|w| ..)` method takes [`perfctr2::W`](W) writer structure"]
impl crate::Writable for PERFCTR2_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff;
}
Expand Down
11 changes: 1 addition & 10 deletions src/busctrl/perfctr3.rs
Original file line number Diff line number Diff line change
Expand Up @@ -28,16 +28,6 @@ impl W {
pub fn perfctr3(&mut self) -> PERFCTR3_W<PERFCTR3_SPEC> {
PERFCTR3_W::new(self, 0)
}
#[doc = r" Writes raw bits to the register."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = "Bus fabric performance counter 3
Expand All @@ -50,6 +40,7 @@ impl crate::RegisterSpec for PERFCTR3_SPEC {
impl crate::Readable for PERFCTR3_SPEC {}
#[doc = "`write(|w| ..)` method takes [`perfctr3::W`](W) writer structure"]
impl crate::Writable for PERFCTR3_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0x00ff_ffff;
}
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15 changes: 3 additions & 12 deletions src/busctrl/perfsel0.rs
Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,6 @@
pub type R = crate::R<PERFSEL0_SPEC>;
#[doc = "Register `PERFSEL0` writer"]
pub type W = crate::W<PERFSEL0_SPEC>;
#[doc = "Field `PERFSEL0` reader - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
pub type PERFSEL0_R = crate::FieldReader<PERFSEL0_A>;
#[doc = "Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
Value on reset: 31"]
Expand Down Expand Up @@ -60,6 +58,8 @@ impl From<PERFSEL0_A> for u8 {
impl crate::FieldSpec for PERFSEL0_A {
type Ux = u8;
}
#[doc = "Field `PERFSEL0` reader - Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
pub type PERFSEL0_R = crate::FieldReader<PERFSEL0_A>;
impl PERFSEL0_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
Expand Down Expand Up @@ -311,16 +311,6 @@ impl W {
pub fn perfsel0(&mut self) -> PERFSEL0_W<PERFSEL0_SPEC> {
PERFSEL0_W::new(self, 0)
}
#[doc = r" Writes raw bits to the register."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = "Bus fabric performance event select for PERFCTR0
Expand All @@ -333,6 +323,7 @@ impl crate::RegisterSpec for PERFSEL0_SPEC {
impl crate::Readable for PERFSEL0_SPEC {}
#[doc = "`write(|w| ..)` method takes [`perfsel0::W`](W) writer structure"]
impl crate::Writable for PERFSEL0_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
Expand Down
15 changes: 3 additions & 12 deletions src/busctrl/perfsel1.rs
Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,6 @@
pub type R = crate::R<PERFSEL1_SPEC>;
#[doc = "Register `PERFSEL1` writer"]
pub type W = crate::W<PERFSEL1_SPEC>;
#[doc = "Field `PERFSEL1` reader - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
pub type PERFSEL1_R = crate::FieldReader<PERFSEL1_A>;
#[doc = "Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
Value on reset: 31"]
Expand Down Expand Up @@ -60,6 +58,8 @@ impl From<PERFSEL1_A> for u8 {
impl crate::FieldSpec for PERFSEL1_A {
type Ux = u8;
}
#[doc = "Field `PERFSEL1` reader - Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
pub type PERFSEL1_R = crate::FieldReader<PERFSEL1_A>;
impl PERFSEL1_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
Expand Down Expand Up @@ -311,16 +311,6 @@ impl W {
pub fn perfsel1(&mut self) -> PERFSEL1_W<PERFSEL1_SPEC> {
PERFSEL1_W::new(self, 0)
}
#[doc = r" Writes raw bits to the register."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = "Bus fabric performance event select for PERFCTR1
Expand All @@ -333,6 +323,7 @@ impl crate::RegisterSpec for PERFSEL1_SPEC {
impl crate::Readable for PERFSEL1_SPEC {}
#[doc = "`write(|w| ..)` method takes [`perfsel1::W`](W) writer structure"]
impl crate::Writable for PERFSEL1_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
Expand Down
15 changes: 3 additions & 12 deletions src/busctrl/perfsel2.rs
Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,6 @@
pub type R = crate::R<PERFSEL2_SPEC>;
#[doc = "Register `PERFSEL2` writer"]
pub type W = crate::W<PERFSEL2_SPEC>;
#[doc = "Field `PERFSEL2` reader - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
pub type PERFSEL2_R = crate::FieldReader<PERFSEL2_A>;
#[doc = "Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
Value on reset: 31"]
Expand Down Expand Up @@ -60,6 +58,8 @@ impl From<PERFSEL2_A> for u8 {
impl crate::FieldSpec for PERFSEL2_A {
type Ux = u8;
}
#[doc = "Field `PERFSEL2` reader - Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar."]
pub type PERFSEL2_R = crate::FieldReader<PERFSEL2_A>;
impl PERFSEL2_R {
#[doc = "Get enumerated values variant"]
#[inline(always)]
Expand Down Expand Up @@ -311,16 +311,6 @@ impl W {
pub fn perfsel2(&mut self) -> PERFSEL2_W<PERFSEL2_SPEC> {
PERFSEL2_W::new(self, 0)
}
#[doc = r" Writes raw bits to the register."]
#[doc = r""]
#[doc = r" # Safety"]
#[doc = r""]
#[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.bits = bits;
self
}
}
#[doc = "Bus fabric performance event select for PERFCTR2
Expand All @@ -333,6 +323,7 @@ impl crate::RegisterSpec for PERFSEL2_SPEC {
impl crate::Readable for PERFSEL2_SPEC {}
#[doc = "`write(|w| ..)` method takes [`perfsel2::W`](W) writer structure"]
impl crate::Writable for PERFSEL2_SPEC {
type Safety = crate::Unsafe;
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
}
Expand Down
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