Update svd2rust to 0.30.2 and regenerate code

src/adc.rs

@@ -23,42 +23,90 @@ pub struct RegisterBlock {
  #[doc = "0x20 - Interrupt status after masking & forcing"]
  pub ints: INTS,
 }
-#[doc = "CS (rw) register accessor: an alias for `Reg<CS_SPEC>`"]
+#[doc = "CS (rw) register accessor: ADC Control and Status 
+
+You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). 
+
+For information about available fields see [`mod@cs`]
+module"]
 pub type CS = crate::Reg<cs::CS_SPEC>;
 #[doc = "ADC Control and Status"]
 pub mod cs;
-#[doc = "RESULT (r) register accessor: an alias for `Reg<RESULT_SPEC>`"]
+#[doc = "RESULT (r) register accessor: Result of most recent ADC conversion 
+
+You can [`read`](crate::generic::Reg::read) this register and get [`result::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). 
+
+For information about available fields see [`mod@result`]
+module"]
 pub type RESULT = crate::Reg<result::RESULT_SPEC>;
 #[doc = "Result of most recent ADC conversion"]
 pub mod result;
-#[doc = "FCS (rw) register accessor: an alias for `Reg<FCS_SPEC>`"]
+#[doc = "FCS (rw) register accessor: FIFO control and status 
+
+You can [`read`](crate::generic::Reg::read) this register and get [`fcs::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fcs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). 
+
+For information about available fields see [`mod@fcs`]
+module"]
 pub type FCS = crate::Reg<fcs::FCS_SPEC>;
 #[doc = "FIFO control and status"]
 pub mod fcs;
-#[doc = "FIFO (r) register accessor: an alias for `Reg<FIFO_SPEC>`"]
+#[doc = "FIFO (r) register accessor: Conversion result FIFO 
+
+You can [`read`](crate::generic::Reg::read) this register and get [`fifo::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). 
+
+For information about available fields see [`mod@fifo`]
+module"]
 pub type FIFO = crate::Reg<fifo::FIFO_SPEC>;
 #[doc = "Conversion result FIFO"]
 pub mod fifo;
-#[doc = "DIV (rw) register accessor: an alias for `Reg<DIV_SPEC>`"]
+#[doc = "DIV (rw) register accessor: Clock divider. If non-zero, CS_START_MANY will start conversions 
+ at regular intervals rather than back-to-back. 
+ The divider is reset when either of these fields are written. 
+ Total period is 1 + INT + FRAC / 256 
+
+You can [`read`](crate::generic::Reg::read) this register and get [`div::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). 
+
+For information about available fields see [`mod@div`]
+module"]
 pub type DIV = crate::Reg<div::DIV_SPEC>;
 #[doc = "Clock divider. If non-zero, CS_START_MANY will start conversions 
  at regular intervals rather than back-to-back. 
  The divider is reset when either of these fields are written. 
  Total period is 1 + INT + FRAC / 256"]
 pub mod div;
-#[doc = "INTR (r) register accessor: an alias for `Reg<INTR_SPEC>`"]
+#[doc = "INTR (r) register accessor: Raw Interrupts 
+
+You can [`read`](crate::generic::Reg::read) this register and get [`intr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). 
+
+For information about available fields see [`mod@intr`]
+module"]
 pub type INTR = crate::Reg<intr::INTR_SPEC>;
 #[doc = "Raw Interrupts"]
 pub mod intr;
-#[doc = "INTE (rw) register accessor: an alias for `Reg<INTE_SPEC>`"]
+#[doc = "INTE (rw) register accessor: Interrupt Enable 
+
+You can [`read`](crate::generic::Reg::read) this register and get [`inte::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`inte::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). 
+
+For information about available fields see [`mod@inte`]
+module"]
 pub type INTE = crate::Reg<inte::INTE_SPEC>;
 #[doc = "Interrupt Enable"]
 pub mod inte;
-#[doc = "INTF (rw) register accessor: an alias for `Reg<INTF_SPEC>`"]
+#[doc = "INTF (rw) register accessor: Interrupt Force 
+
+You can [`read`](crate::generic::Reg::read) this register and get [`intf::R`]. You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`intf::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api). 
+
+For information about available fields see [`mod@intf`]
+module"]
 pub type INTF = crate::Reg<intf::INTF_SPEC>;
 #[doc = "Interrupt Force"]
 pub mod intf;
-#[doc = "INTS (r) register accessor: an alias for `Reg<INTS_SPEC>`"]
+#[doc = "INTS (r) register accessor: Interrupt status after masking &amp; forcing 
+
+You can [`read`](crate::generic::Reg::read) this register and get [`ints::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api). 
+
+For information about available fields see [`mod@ints`]
+module"]
 pub type INTS = crate::Reg<ints::INTS_SPEC>;
 #[doc = "Interrupt status after masking &amp; forcing"]
 pub mod ints;

src/adc/cs.rs

@@ -1,57 +1,25 @@
 #[doc = "Register `CS` reader"]
-pub struct R(crate::R<CS_SPEC>);
-impl core::ops::Deref for R {
- type Target = crate::R<CS_SPEC>;
- #[inline(always)]
- fn deref(&self) -> &Self::Target {
- &self.0
- }
-}
-impl From<crate::R<CS_SPEC>> for R {
- #[inline(always)]
- fn from(reader: crate::R<CS_SPEC>) -> Self {
- R(reader)
- }
-}
+pub type R = crate::R<CS_SPEC>;
 #[doc = "Register `CS` writer"]
-pub struct W(crate::W<CS_SPEC>);
-impl core::ops::Deref for W {
- type Target = crate::W<CS_SPEC>;
- #[inline(always)]
- fn deref(&self) -> &Self::Target {
- &self.0
- }
-}
-impl core::ops::DerefMut for W {
- #[inline(always)]
- fn deref_mut(&mut self) -> &mut Self::Target {
- &mut self.0
- }
-}
-impl From<crate::W<CS_SPEC>> for W {
- #[inline(always)]
- fn from(writer: crate::W<CS_SPEC>) -> Self {
- W(writer)
- }
-}
+pub type W = crate::W<CS_SPEC>;
 #[doc = "Field `EN` reader - Power on ADC and enable its clock. 
  1 - enabled. 0 - disabled."]
 pub type EN_R = crate::BitReader;
 #[doc = "Field `EN` writer - Power on ADC and enable its clock. 
  1 - enabled. 0 - disabled."]
-pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, CS_SPEC, O>;
+pub type EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
 #[doc = "Field `TS_EN` reader - Power on temperature sensor. 1 - enabled. 0 - disabled."]
 pub type TS_EN_R = crate::BitReader;
 #[doc = "Field `TS_EN` writer - Power on temperature sensor. 1 - enabled. 0 - disabled."]
-pub type TS_EN_W<'a, const O: u8> = crate::BitWriter<'a, CS_SPEC, O>;
+pub type TS_EN_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
 #[doc = "Field `START_ONCE` reader - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
 pub type START_ONCE_R = crate::BitReader;
 #[doc = "Field `START_ONCE` writer - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
-pub type START_ONCE_W<'a, const O: u8> = crate::BitWriter<'a, CS_SPEC, O>;
+pub type START_ONCE_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
 #[doc = "Field `START_MANY` reader - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
 pub type START_MANY_R = crate::BitReader;
 #[doc = "Field `START_MANY` writer - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
-pub type START_MANY_W<'a, const O: u8> = crate::BitWriter<'a, CS_SPEC, O>;
+pub type START_MANY_W<'a, REG, const O: u8> = crate::BitWriter<'a, REG, O>;
 #[doc = "Field `READY` reader - 1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed. 
  0 whilst conversion in progress."]
 pub type READY_R = crate::BitReader;
@@ -60,11 +28,11 @@ pub type ERR_R = crate::BitReader;
 #[doc = "Field `ERR_STICKY` reader - Some past ADC conversion encountered an error. Write 1 to clear."]
 pub type ERR_STICKY_R = crate::BitReader;
 #[doc = "Field `ERR_STICKY` writer - Some past ADC conversion encountered an error. Write 1 to clear."]
-pub type ERR_STICKY_W<'a, const O: u8> = crate::BitWriter1C<'a, CS_SPEC, O>;
+pub type ERR_STICKY_W<'a, REG, const O: u8> = crate::BitWriter1C<'a, REG, O>;
 #[doc = "Field `AINSEL` reader - Select analog mux input. Updated automatically in round-robin mode."]
 pub type AINSEL_R = crate::FieldReader;
 #[doc = "Field `AINSEL` writer - Select analog mux input. Updated automatically in round-robin mode."]
-pub type AINSEL_W<'a, const O: u8> = crate::FieldWriter<'a, CS_SPEC, 3, O>;
+pub type AINSEL_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 3, O>;
 #[doc = "Field `RROBIN` reader - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. 
  Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. 
  The first channel to be sampled will be the one currently indicated by AINSEL. 
@@ -74,7 +42,7 @@ pub type RROBIN_R = crate::FieldReader;
  Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion. 
  The first channel to be sampled will be the one currently indicated by AINSEL. 
  AINSEL will be updated after each conversion with the newly-selected channel."]
-pub type RROBIN_W<'a, const O: u8> = crate::FieldWriter<'a, CS_SPEC, 5, O>;
+pub type RROBIN_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 5, O>;
 impl R {
  #[doc = "Bit 0 - Power on ADC and enable its clock. 
  1 - enabled. 0 - disabled."]
@@ -132,37 +100,37 @@ impl W {
  1 - enabled. 0 - disabled."]
  #[inline(always)]
  #[must_use]
- pub fn en(&mut self) -> EN_W<0> {
+ pub fn en(&mut self) -> EN_W<CS_SPEC, 0> {
  EN_W::new(self)
  }
  #[doc = "Bit 1 - Power on temperature sensor. 1 - enabled. 0 - disabled."]
  #[inline(always)]
  #[must_use]
- pub fn ts_en(&mut self) -> TS_EN_W<1> {
+ pub fn ts_en(&mut self) -> TS_EN_W<CS_SPEC, 1> {
  TS_EN_W::new(self)
  }
  #[doc = "Bit 2 - Start a single conversion. Self-clearing. Ignored if start_many is asserted."]
  #[inline(always)]
  #[must_use]
- pub fn start_once(&mut self) -> START_ONCE_W<2> {
+ pub fn start_once(&mut self) -> START_ONCE_W<CS_SPEC, 2> {
  START_ONCE_W::new(self)
  }
  #[doc = "Bit 3 - Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes."]
  #[inline(always)]
  #[must_use]
- pub fn start_many(&mut self) -> START_MANY_W<3> {
+ pub fn start_many(&mut self) -> START_MANY_W<CS_SPEC, 3> {
  START_MANY_W::new(self)
  }
  #[doc = "Bit 10 - Some past ADC conversion encountered an error. Write 1 to clear."]
  #[inline(always)]
  #[must_use]
- pub fn err_sticky(&mut self) -> ERR_STICKY_W<10> {
+ pub fn err_sticky(&mut self) -> ERR_STICKY_W<CS_SPEC, 10> {
  ERR_STICKY_W::new(self)
  }
  #[doc = "Bits 12:14 - Select analog mux input. Updated automatically in round-robin mode."]
  #[inline(always)]
  #[must_use]
- pub fn ainsel(&mut self) -> AINSEL_W<12> {
+ pub fn ainsel(&mut self) -> AINSEL_W<CS_SPEC, 12> {
  AINSEL_W::new(self)
  }
  #[doc = "Bits 16:20 - Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable. 
@@ -171,32 +139,31 @@ impl W {
  AINSEL will be updated after each conversion with the newly-selected channel."]
  #[inline(always)]
  #[must_use]
- pub fn rrobin(&mut self) -> RROBIN_W<16> {
+ pub fn rrobin(&mut self) -> RROBIN_W<CS_SPEC, 16> {
  RROBIN_W::new(self)
  }
- #[doc = "Writes raw bits to the register."]
+ #[doc = r" Writes raw bits to the register."]
+ #[doc = r""]
+ #[doc = r" # Safety"]
+ #[doc = r""]
+ #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
  #[inline(always)]
  pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
- self.0.bits(bits);
+ self.bits = bits;
  self
  }
 }
 #[doc = "ADC Control and Status 
 
-This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 
-
-For information about available fields see [cs](index.html) module"]
+You can [`read`](crate::generic::Reg::read) this register and get [`cs::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cs::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct CS_SPEC;
 impl crate::RegisterSpec for CS_SPEC {
  type Ux = u32;
 }
-#[doc = "`read()` method returns [cs::R](R) reader structure"]
-impl crate::Readable for CS_SPEC {
- type Reader = R;
-}
-#[doc = "`write(|w| ..)` method takes [cs::W](W) writer structure"]
+#[doc = "`read()` method returns [`cs::R`](R) reader structure"]
+impl crate::Readable for CS_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`cs::W`](W) writer structure"]
 impl crate::Writable for CS_SPEC {
- type Writer = W;
  const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
  const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0400;
 }

src/adc/div.rs

@@ -1,47 +1,15 @@
 #[doc = "Register `DIV` reader"]
-pub struct R(crate::R<DIV_SPEC>);
-impl core::ops::Deref for R {
- type Target = crate::R<DIV_SPEC>;
- #[inline(always)]
- fn deref(&self) -> &Self::Target {
- &self.0
- }
-}
-impl From<crate::R<DIV_SPEC>> for R {
- #[inline(always)]
- fn from(reader: crate::R<DIV_SPEC>) -> Self {
- R(reader)
- }
-}
+pub type R = crate::R<DIV_SPEC>;
 #[doc = "Register `DIV` writer"]
-pub struct W(crate::W<DIV_SPEC>);
-impl core::ops::Deref for W {
- type Target = crate::W<DIV_SPEC>;
- #[inline(always)]
- fn deref(&self) -> &Self::Target {
- &self.0
- }
-}
-impl core::ops::DerefMut for W {
- #[inline(always)]
- fn deref_mut(&mut self) -> &mut Self::Target {
- &mut self.0
- }
-}
-impl From<crate::W<DIV_SPEC>> for W {
- #[inline(always)]
- fn from(writer: crate::W<DIV_SPEC>) -> Self {
- W(writer)
- }
-}
+pub type W = crate::W<DIV_SPEC>;
 #[doc = "Field `FRAC` reader - Fractional part of clock divisor. First-order delta-sigma."]
 pub type FRAC_R = crate::FieldReader;
 #[doc = "Field `FRAC` writer - Fractional part of clock divisor. First-order delta-sigma."]
-pub type FRAC_W<'a, const O: u8> = crate::FieldWriter<'a, DIV_SPEC, 8, O>;
+pub type FRAC_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 8, O>;
 #[doc = "Field `INT` reader - Integer part of clock divisor."]
 pub type INT_R = crate::FieldReader<u16>;
 #[doc = "Field `INT` writer - Integer part of clock divisor."]
-pub type INT_W<'a, const O: u8> = crate::FieldWriter<'a, DIV_SPEC, 16, O, u16>;
+pub type INT_W<'a, REG, const O: u8> = crate::FieldWriter<'a, REG, 16, O, u16>;
 impl R {
  #[doc = "Bits 0:7 - Fractional part of clock divisor. First-order delta-sigma."]
  #[inline(always)]
@@ -58,19 +26,23 @@ impl W {
  #[doc = "Bits 0:7 - Fractional part of clock divisor. First-order delta-sigma."]
  #[inline(always)]
  #[must_use]
- pub fn frac(&mut self) -> FRAC_W<0> {
+ pub fn frac(&mut self) -> FRAC_W<DIV_SPEC, 0> {
  FRAC_W::new(self)
  }
  #[doc = "Bits 8:23 - Integer part of clock divisor."]
  #[inline(always)]
  #[must_use]
- pub fn int(&mut self) -> INT_W<8> {
+ pub fn int(&mut self) -> INT_W<DIV_SPEC, 8> {
  INT_W::new(self)
  }
- #[doc = "Writes raw bits to the register."]
+ #[doc = r" Writes raw bits to the register."]
+ #[doc = r""]
+ #[doc = r" # Safety"]
+ #[doc = r""]
+ #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
  #[inline(always)]
  pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
- self.0.bits(bits);
+ self.bits = bits;
  self
  }
 }
@@ -79,20 +51,15 @@ impl W {
  The divider is reset when either of these fields are written. 
  Total period is 1 + INT + FRAC / 256 
 
-This register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api). 
-
-For information about available fields see [div](index.html) module"]
+You can [`read`](crate::generic::Reg::read) this register and get [`div::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`div::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
 pub struct DIV_SPEC;
 impl crate::RegisterSpec for DIV_SPEC {
  type Ux = u32;
 }
-#[doc = "`read()` method returns [div::R](R) reader structure"]
-impl crate::Readable for DIV_SPEC {
- type Reader = R;
-}
-#[doc = "`write(|w| ..)` method takes [div::W](W) writer structure"]
+#[doc = "`read()` method returns [`div::R`](R) reader structure"]
+impl crate::Readable for DIV_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`div::W`](W) writer structure"]
 impl crate::Writable for DIV_SPEC {
- type Writer = W;
  const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
  const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
 }