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  • lowRISC
  • Cambridge, UK

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  1. ibex ibex Public

    Forked from lowRISC/ibex

    Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

    SystemVerilog 1 1

  2. opentitan opentitan Public

    Forked from lowRISC/opentitan

    OpenTitan: Open source silicon root of trust

    SystemVerilog

  3. yosys yosys Public

    Forked from YosysHQ/yosys

    Yosys Open SYnthesis Suite

    C++ 1

  4. fusesoc fusesoc Public

    Forked from olofk/fusesoc

    Package manager and build abstraction tool for FPGA/ASIC development

    Python 1

  5. riscv-isa-sim riscv-isa-sim Public

    Forked from riscv-software-src/riscv-isa-sim

    Spike, a RISC-V ISA Simulator

    C 1

  6. acov acov Public

    Forked from ArgonDesign/acov

    Generator of functional coverage tracking code for Verilog projects

    Haskell 1 2