map asm! ops to unimplemented! on non ARM targets

rust-embedded · Dec 23, 2017 · 875ee38 · 875ee38
1 parent 9a80bae
commit 875ee38
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Showing 12 changed files with 183 additions and 191 deletions.
diff --git a/src/asm.rs b/src/asm.rs
@@ -7,74 +7,57 @@
 /// cause an exception
 #[inline(always)]
 pub fn bkpt() {
-    #[cfg(target_arch = "arm")]
-    unsafe {
-        asm!("bkpt"
-             :
-             :
-             :
-             : "volatile");
+    match () {
+        #[cfg(target_arch = "arm")]
+        () => unsafe { asm!("bkpt" :::: "volatile") },
+        #[cfg(not(target_arch = "arm"))]
+        () => unimplemented!(),
     }
 }
 
 /// A no-operation. Useful to prevent delay loops from being optimized away.
-#[inline(always)]
+#[inline]
 pub fn nop() {
-    unsafe {
-        asm!("nop"
-             :
-             :
-             :
-             : "volatile");
+    match () {
+        #[cfg(target_arch = "arm")]
+        () => unsafe { asm!("nop" :::: "volatile") },
+        #[cfg(not(target_arch = "arm"))]
+        () => unimplemented!(),
     }
 }
 /// Wait For Event
-#[inline(always)]
+#[inline]
 pub fn wfe() {
     match () {
         #[cfg(target_arch = "arm")]
-        () => unsafe {
-            asm!("wfe"
-                 :
-                 :
-                 :
-                 : "volatile")
-        },
+        () => unsafe { asm!("wfe" :::: "volatile") },
         #[cfg(not(target_arch = "arm"))]
-        () => {}
+        () => unimplemented!(),
     }
 }
 
 /// Wait For Interrupt
-#[inline(always)]
+#[inline]
 pub fn wfi() {
     match () {
         #[cfg(target_arch = "arm")]
-        () => unsafe{
-            asm!("wfi"
-                 :
-                 :
-                 :
-                 : "volatile")
-        },
+        () => unsafe { asm!("wfi" :::: "volatile") },
         #[cfg(not(target_arch = "arm"))]
-        () => {}
+        () => unimplemented!(),
     }
 }
 
 /// Instruction Synchronization Barrier
 ///
 /// Flushes the pipeline in the processor, so that all instructions following the `ISB` are fetched
 /// from cache or memory, after the instruction has been completed.
-#[inline(always)]
+#[inline]
 pub fn isb() {
     match () {
         #[cfg(target_arch = "arm")]
-        () => unsafe {
-            asm!("isb 0xF" : : : "memory" : "volatile");
-        },
+        () => unsafe { asm!("isb 0xF" : : : "memory" : "volatile") },
         #[cfg(not(target_arch = "arm"))]
-        () => {}
+        () => unimplemented!(),
     }
 }
 
@@ -86,15 +69,13 @@ pub fn isb() {
 ///
 ///  * any explicit memory access made before this instruction is complete
 ///  * all cache and branch predictor maintenance operations before this instruction complete
-#[inline(always)]
+#[inline]
 pub fn dsb() {
     match () {
         #[cfg(target_arch = "arm")]
-        () => unsafe {
-            asm!("dsb 0xF" : : : "memory" : "volatile");
-        },
+        () => unsafe { asm!("dsb 0xF" : : : "memory" : "volatile") },
         #[cfg(not(target_arch = "arm"))]
-        () => {}
+        () => unimplemented!(),
     }
 }
 
@@ -103,14 +84,12 @@ pub fn dsb() {
 /// Ensures that all explicit memory accesses that appear in program order before the `DMB`
 /// instruction are observed before any explicit memory accesses that appear in program order
 /// after the `DMB` instruction.
-#[inline(always)]
+#[inline]
 pub fn dmb() {
     match () {
         #[cfg(target_arch = "arm")]
-        () => unsafe {
-            asm!("dmb 0xF" : : : "memory" : "volatile");
-        },
+        () => unsafe { asm!("dmb 0xF" : : : "memory" : "volatile") },
         #[cfg(not(target_arch = "arm"))]
-        () => {}
+        () => unimplemented!(),
     }
 }
diff --git a/src/interrupt.rs b/src/interrupt.rs
@@ -3,19 +3,15 @@
 pub use bare_metal::{CriticalSection, Mutex, Nr};
 
 /// Disables all interrupts
-#[inline(always)]
+#[inline]
 pub fn disable() {
     match () {
         #[cfg(target_arch = "arm")]
         () => unsafe {
-            asm!("cpsid i"
-                 :
-                 :
-                 : "memory"
-                 : "volatile");
+            asm!("cpsid i" ::: "memory" : "volatile");
         },
         #[cfg(not(target_arch = "arm"))]
-        () => {}
+        () => unimplemented!(),
     }
 }
 
@@ -24,19 +20,13 @@ pub fn disable() {
 /// # Safety
 ///
 /// - Do not call this function inside an `interrupt::free` critical section
-#[inline(always)]
+#[inline]
 pub unsafe fn enable() {
     match () {
         #[cfg(target_arch = "arm")]
-        () => {
-            asm!("cpsie i"
-                 :
-                 :
-                 : "memory"
-                 : "volatile");
-        }
+        () => asm!("cpsie i" ::: "memory" : "volatile"),
         #[cfg(not(target_arch = "arm"))]
-        () => {}
+        () => unimplemented!(),
     }
 }
 

diff --git a/src/register/apsr.rs b/src/register/apsr.rs
@@ -39,15 +39,18 @@ impl Apsr {
 }
 
 /// Reads the CPU register
-#[inline(always)]
+#[inline]
 pub fn read() -> Apsr {
-    let r: u32;
-    unsafe {
-        asm!("mrs $0, APSR"
-             : "=r"(r)
-             :
-             :
-             : "volatile");
+    match () {
+        #[cfg(target_arch = "arm")]
+        () => {
+            let r: u32;
+            unsafe {
+                asm!("mrs $0, APSR" : "=r"(r) ::: "volatile");
+            }
+            Apsr { bits: r }
+        }
+        #[cfg(not(target_arch = "arm"))]
+        () => unimplemented!(),
     }
-    Apsr { bits: r }
 }
diff --git a/src/register/basepri.rs b/src/register/basepri.rs
@@ -1,25 +1,29 @@
 //! Base Priority Mask Register
 
 /// Reads the CPU register
-#[inline(always)]
+#[inline]
 pub fn read() -> u8 {
-    let r: u32;
-    unsafe {
-        asm!("mrs $0, BASEPRI"
-             : "=r"(r)
-             :
-             :
-             : "volatile");
+    match () {
+        #[cfg(target_arch = "arm")]
+        () => {
+            let r: u32;
+            unsafe {
+                asm!("mrs $0, BASEPRI" : "=r"(r) ::: "volatile");
+            }
+            r as u8
+        }
+        #[cfg(not(target_arch = "arm"))]
+        () => unimplemented!(),
     }
-    r as u8
 }
 
 /// Writes to the CPU register
-#[inline(always)]
-pub unsafe fn write(basepri: u8) {
-    asm!("msr BASEPRI, $0"
-         :
-         : "r"(basepri)
-         : "memory"
-         : "volatile");
+#[inline]
+pub unsafe fn write(_basepri: u8) {
+    match () {
+        #[cfg(target_arch = "arm")]
+        () => asm!("msr BASEPRI, $0" :: "r"(_basepri) : "memory" : "volatile"),
+        #[cfg(not(target_arch = "arm"))]
+        () => unimplemented!(),
+    }
 }
diff --git a/src/register/basepri_max.rs b/src/register/basepri_max.rs
@@ -4,13 +4,14 @@
 ///
 /// - `basepri != 0` AND `basepri::read() == 0`, OR
 /// - `basepri != 0` AND `basepri < basepri::read()`
-#[inline(always)]
-pub fn write(basepri: u8) {
-    unsafe {
-        asm!("msr BASEPRI_MAX, $0"
-             :
-             : "r"(basepri)
-             : "memory"
-             : "volatile");
+#[inline]
+pub fn write(_basepri: u8) {
+    match () {
+        #[cfg(target_arch = "arm")]
+        () => unsafe {
+            asm!("msr BASEPRI_MAX, $0" :: "r"(_basepri) : "memory" : "volatile");
+        },
+        #[cfg(not(target_arch = "arm"))]
+        () => unimplemented!(),
     }
 }
diff --git a/src/register/control.rs b/src/register/control.rs
@@ -104,15 +104,16 @@ impl Fpca {
 }
 
 /// Reads the CPU register
-#[inline(always)]
+#[inline]
 pub fn read() -> Control {
-    let r: u32;
-    unsafe {
-        asm!("mrs $0, CONTROL"
-             : "=r"(r)
-             :
-             :
-             : "volatile");
+    match () {
+        #[cfg(target_arch = "arm")]
+        () => {
+            let r: u32;
+            unsafe { asm!("mrs $0, CONTROL" : "=r"(r) ::: "volatile") }
+            Control { bits: r }
+        }
+        #[cfg(not(target_arch = "arm"))]
+        () => unimplemented!(),
     }
-    Control { bits: r }
 }
diff --git a/src/register/faultmask.rs b/src/register/faultmask.rs
@@ -22,19 +22,20 @@ impl Faultmask {
 }
 
 /// Reads the CPU register
-#[inline(always)]
+#[inline]
 pub fn read() -> Faultmask {
-    let r: u32;
-    unsafe {
-        asm!("mrs $0, FAULTMASK"
-             : "=r"(r)
-             :
-             :
-             : "volatile");
-    }
-    if r & (1 << 0) == (1 << 0) {
-        Faultmask::Inactive
-    } else {
-        Faultmask::Active
+    match () {
+        #[cfg(target_arch = "arm")]
+        () => {
+            let r: u32;
+            unsafe { asm!("mrs $0, FAULTMASK" : "=r"(r) ::: "volatile") }
+            if r & (1 << 0) == (1 << 0) {
+                Faultmask::Inactive
+            } else {
+                Faultmask::Active
+            }
+        }
+        #[cfg(not(target_arch = "arm"))]
+        () => unimplemented!(),
     }
 }
diff --git a/src/register/lr.rs b/src/register/lr.rs
@@ -1,25 +1,28 @@
 //! Link register
 
 /// Reads the CPU register
-#[inline(always)]
+#[inline]
 pub fn read() -> u32 {
-    let r: u32;
-    unsafe {
-        asm!("mov $0,R14"
-             : "=r"(r)
-             :
-             :
-             : "volatile");
+    match () {
+        #[cfg(target_arch = "arm")]
+        () => {
+            let r: u32;
+            unsafe { asm!("mov $0,R14" : "=r"(r) ::: "volatile") }
+            r
+        }
+        #[cfg(not(target_arch = "arm"))]
+        () => unimplemented!(),
     }
-    r
 }
 
 /// Writes `bits` to the CPU register
-#[inline(always)]
+#[cfg_attr(not(target_arch = "arm"), allow(unused_variables))]
+#[inline]
 pub unsafe fn write(bits: u32) {
-    asm!("mov R14,$0"
-         :
-         : "r"(bits)
-         :
-         : "volatile");
+    match () {
+        #[cfg(target_arch = "arm")]
+        () => asm!("mov R14,$0" :: "r"(bits) :: "volatile"),
+        #[cfg(not(target_arch = "arm"))]
+        () => unimplemented!(),
+    }
 }