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Add ITNS field to NVIC peripheral #422

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Merged
merged 2 commits into from
Nov 12, 2022
Merged

Add ITNS field to NVIC peripheral #422

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05ddb44
add itns field to NVIC perph
sphw Feb 16, 2022
9bff0c8
fix and cleanup offsets in nvic
sphw Mar 15, 2022
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9 changes: 8 additions & 1 deletion src/peripheral/nvic.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -33,9 +33,16 @@ pub struct RegisterBlock {
/// Interrupt Active Bit (not present on Cortex-M0 variants)
#[cfg(not(armv6m))]
pub iabr: [RO<u32>; 16],
#[cfg(armv6m)]
#[cfg(any(armv6m, armv8m))]
_reserved4: [u32; 16],

#[cfg(armv8m)]
/// Interrupt Target Non-secure (only present on Arm v8-M)
pub itns: [RW<u32>; 16],
#[cfg(armv8m)]
_reserved5: [u32; 32],

#[cfg(not(armv8m))]
_reserved5: [u32; 48],

/// Interrupt Priority
Expand Down