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Expose configuration of the SEVONPEND bit within the System Control Register (SCR) #539

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Merged
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Jun 30, 2024
Merged

Expose configuration of the SEVONPEND bit within the System Control Register (SCR) #539

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20 changes: 20 additions & 0 deletions cortex-m/src/peripheral/scb.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -832,6 +832,26 @@ impl SCB {
}
}

const SCB_SCR_SEVONPEND: u32 = 0x1 << 4;

impl SCB {
/// Set the SEVONPEND bit in the SCR register
#[inline]
pub fn set_sevonpend(&mut self) {
unsafe {
self.scr.modify(|scr| scr | SCB_SCR_SEVONPEND);
}
}

/// Clear the SEVONPEND bit in the SCR register
#[inline]
pub fn clear_sevonpend(&mut self) {
unsafe {
self.scr.modify(|scr| scr & !SCB_SCR_SEVONPEND);
}
}
}

const SCB_AIRCR_VECTKEY: u32 = 0x05FA << 16;
const SCB_AIRCR_PRIGROUP_MASK: u32 = 0x7 << 8;
const SCB_AIRCR_SYSRESETREQ: u32 = 1 << 2;
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