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Merge pull request #270 from hegza/pr/write-pcounters
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riscv: make mcycle & minstret writable
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romancardenas authored Feb 21, 2025
2 parents 6b57558 + 75c0048 commit 95cfb90
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5 changes: 5 additions & 0 deletions riscv/CHANGELOG.md
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Expand Up @@ -7,6 +7,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).

## [Unreleased]

### Added

- CSR helper macro `write_composite_csr` for writing 64-bit CSRs on 32-bit targets.
- Write utilities for `mcycle`, `minstret`

## [v0.13.0] - 2025-02-18

### Added
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24 changes: 24 additions & 0 deletions riscv/src/register/macros.rs
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Expand Up @@ -449,6 +449,30 @@ macro_rules! read_composite_csr {
};
}

/// Convenience macro to write a composite value to a CSR register.
///
/// - `RV32`: writes 32-bits into `hi` and 32-bits into `lo` to create a 64-bit value
/// - `RV64`: writes a 64-bit value into `lo`
#[macro_export]
macro_rules! write_composite_csr {
($hi:expr, $lo:expr) => {
/// Writes the CSR as a 64-bit value
#[inline]
pub unsafe fn write64(bits: u64) {
match () {
#[cfg(target_arch = "riscv32")]
() => {
$hi((bits >> 32) as usize);
$lo(bits as usize);
}

#[cfg(not(target_arch = "riscv32"))]
() => $lo(bits as usize),
}
}
};
}

macro_rules! set_pmp {
() => {
/// Set the pmp configuration corresponding to the index.
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2 changes: 2 additions & 0 deletions riscv/src/register/mcycle.rs
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@@ -1,4 +1,6 @@
//! mcycle register
read_csr_as_usize!(0xB00);
write_csr_as_usize!(0xB00);
read_composite_csr!(super::mcycleh::read(), read());
write_composite_csr!(super::mcycleh::write, write);
1 change: 1 addition & 0 deletions riscv/src/register/mcycleh.rs
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@@ -1,3 +1,4 @@
//! mcycleh register
read_csr_as_usize_rv32!(0xB80);
write_csr_as_usize_rv32!(0xB80);
2 changes: 2 additions & 0 deletions riscv/src/register/minstret.rs
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@@ -1,4 +1,6 @@
//! minstret register
read_csr_as_usize!(0xB02);
write_csr_as_usize!(0xB02);
read_composite_csr!(super::minstreth::read(), read());
write_composite_csr!(super::minstreth::write, write);
1 change: 1 addition & 0 deletions riscv/src/register/minstreth.rs
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@@ -1,3 +1,4 @@
//! minstreth register
read_csr_as_usize_rv32!(0xB82);
write_csr_as_usize_rv32!(0xB82);

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