Feature-gate trap-related code in riscv #345
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This PR is ready for a review. Fixes #344 Fixes rust-embedded/svd2rust#948 (after releasing a new version) |
| Some(Some(handler)) => handler(#(#handler_input),*), | ||
| _ => #default_handler(#(#handler_input),*), | ||
| } | ||
| _ => { |
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Here, @romancardenas take my words with a grain of salt because I may or may not be allowed/elligible to make reviews in this crate, but seems like the _ arm handles both the external interrupts AND the cases when rt-v-trap is disabled for the core interrupts.
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Yes, that is the idea. If rt-v-trap is enabled, then an assembly vector table is generated for core interrupts. Otherwise, it generates the typical code for a direct trap handler, regardless of whether it is a core or an external interrupt.
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I see! @romancardenas thanks for addressing my reviews :)
Currently,
riscv::pac_enummacro can potentially generate code that refers toriscv-rt. This should be avoided unless explicitly enabled by users.This PR adds the
rtandrt-v-trapfeatures toriscvto fix this bug.Related issues: rust-embedded/svd2rust#948