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Use riscv section for RISC-V targets #856

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Merged
merged 2 commits into from
Oct 21, 2024
Merged

Use riscv section for RISC-V targets #856

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90ef2a6
settings.yaml file for target-specific configurations.
romancardenas Jul 1, 2024
7468bd6
Update riscv CI to 0.12.1
romancardenas Oct 21, 2024
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4 changes: 4 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](https://semver.org/).

## [Unreleased]

- Compatibility with `riscv` 0.12 and `riscv-rt` 0.13
- Add `riscv_config` section in `settings.yaml`
It uses `riscv-pac` traits and standard `riscv-peripheral` peripherals.
- Add `settings.yaml` file for target-specific settings.
- Add warning about indexing register arrays
- Skip generating `.add(0)` and `1 *` in accessors
- Bump MSRV of generated code to 1.76
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