Merge pull request #79 from parched/rust-smulo

Fix signed multiplication with overflow
rust-lang · May 19, 2017 · 5edb164 · 5edb164
2 parents 1ef3b91 + 15d7c54
commit 5edb164
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Showing 2 changed files with 18 additions and 2 deletions.
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3481,11 +3481,11 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) {
       // part.
       unsigned LoSize = VT.getSizeInBits();
       SDValue HiLHS =
-          DAG.getNode(ISD::SRA, dl, VT, RHS,
+          DAG.getNode(ISD::SRA, dl, VT, LHS,
                       DAG.getConstant(LoSize - 1, dl,
                                       TLI.getPointerTy(DAG.getDataLayout())));
       SDValue HiRHS =
-          DAG.getNode(ISD::SRA, dl, VT, LHS,
+          DAG.getNode(ISD::SRA, dl, VT, RHS,
                       DAG.getConstant(LoSize - 1, dl,
                                       TLI.getPointerTy(DAG.getDataLayout())));
 

diff --git a/test/CodeGen/ARM/v6m-smul-with-overflow.ll b/test/CodeGen/ARM/v6m-smul-with-overflow.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s
+
+define i1 @signed_multiplication_did_overflow(i32, i32) {
+; CHECK-LABEL: signed_multiplication_did_overflow:
+entry-block:
+  %2 = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %1)
+  %3 = extractvalue { i32, i1 } %2, 1
+  ret i1 %3
+
+; CHECK: mov    r2, r1
+; CHECK: asrs   r1, r0, #31
+; CHECK: asrs   r3, r2, #31
+; CHECK: bl     __aeabi_lmul
+}
+
+declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)