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backport fixes to LLVM 4.0 ARM codegen bugs #83
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If we got unlucky with register allocation and actual constpool placement, we could end up producing a tTBB_JT with an index that's already been clobbered. Technically, we might be able to fix this situation up with a MOV, but I think the constant islands pass is complex enough without having to deal with more weird edge-cases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297871 91177308-0d34-0410-b5e6-96231b3b80d8
We match a sequence of 3-4 instructions into a tTBB pseudo. One of our checks is that a particular register in that sequence is killed (so it can be clobbered by the pseudo). We weren't noticing if an errant MOV or other instruction had infiltrated the sequence we were walking. If it had, and it defined the register we've already identified as killed, it makes it live across the tBR_JT and thus unclobberable. Notice this case and bail out. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294949 91177308-0d34-0410-b5e6-96231b3b80d8
The pass tries to fix a spill of LR that turns out to be unnecessary. So it removes the tPOP but forgets to remove tPUSH. This causes the stack be misaligned upon returning the function. Thus, remove the tPUSH as well in this case. Differential Revision: https://reviews.llvm.org/D30207 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@295816 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
When synthesized TBB/TBH is expanded, we need to avoid the case of:
BaseReg is redefined after the load of branching target. E.g.:
%R2 = tLEApcrelJT <jt#1>
%R1 = tLDRr %R1, %R2 ==> %R2 = tLEApcrelJT <jt#1>
%R2 = tLDRspi %SP, 12 %R2 = tLDRspi %SP, 12
tBR_JTr %R1 tTBB_JT %R2, %R1
`
Reviewers: jmolloy
Reviewed By: jmolloy
Subscribers: llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D32250
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300870 91177308-0d34-0410-b5e6-96231b3b80d8
Summary: When trying to figure out if MBB could fallthrough to ToMBB (possibly by falling through a bunch of other MBBs) we didn't actually check if there was fallthrough between the last two blocks in the chain. Reviewers: kparzysz, iteratee, MatzeB Reviewed By: kparzysz, iteratee Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D32996 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@302650 91177308-0d34-0410-b5e6-96231b3b80d8
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Nice! |
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Now let me confirm it fixes the nrf51dk bug and I'll open a PR. |
arielb1
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backport fixes to LLVM 4.0 ARM codegen bugs
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So ARM had quite a few codegen bugs on LLVM 4.0 which are fixed on LLVM trunk. This backports 5 of them:
r297871 - ARM: avoid clobbering register in v6 jump-table expansion.
- causes rust-lang/rust#42248
r294949 - [Thumb-1] TBB generation: spot redefinitions of index
r295816 - [ARM] Fix constant islands pass.
r300870 - [Thumb-1] Fix corner cases for compressed jump tables
r302650 - [IfConversion] Add missing check in IfConversion/canFallThroughTo
- blocks rust-lang/rust#39409