Enable cfg miri in analysis

crates/hir-ty/src/mir/eval/shim.rs

@@ -380,6 +380,17 @@ impl Evaluator<'_> {
                 let id = from_bytes!(i64, id.get(self)?);
                 self.exec_syscall(id, rest, destination, locals, span)
             }
+            "sched_getaffinity" => {
+                let [_pid, _set_size, set] = args else {
+                    return Err(MirEvalError::TypeError("libc::write args are not provided"));
+                };
+                let set = Address::from_bytes(set.get(self)?)?;
+                // Only enable core 0 (we are single threaded anyway), which is bitset 0x0000001
+                self.write_memory(set, &[1])?;
+                // return 0 as success
+                self.write_memory_using_ref(destination.addr, destination.size)?.fill(0);
+                Ok(())
+            }
             _ => not_supported!("unknown external function {as_str}"),
         }
     }

crates/project-model/src/rustc_cfg.rs

@@ -22,6 +22,9 @@ pub(crate) fn get(
         }
     }
 
+    // Add miri cfg, which is useful for mir eval in stdlib
+    res.push(CfgFlag::Atom("miri".into()));
+
     match get_rust_cfgs(cargo_toml, target, extra_env) {
         Ok(rustc_cfgs) => {
             tracing::debug!(