@@ -6,7 +6,6 @@ use std::fmt;
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def_reg_class ! {
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Arm ArmInlineAsmRegClass {
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reg,
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- reg_thumb,
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sreg,
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sreg_low16,
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dreg,
@@ -47,7 +46,7 @@ impl ArmInlineAsmRegClass {
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_arch : InlineAsmArch ,
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) -> & ' static [ ( InlineAsmType , Option < & ' static str > ) ] {
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match self {
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- Self :: reg | Self :: reg_thumb => types ! { _: I8 , I16 , I32 , F32 ; } ,
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+ Self :: reg => types ! { _: I8 , I16 , I32 , F32 ; } ,
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Self :: sreg | Self :: sreg_low16 => types ! { "vfp2" : I32 , F32 ; } ,
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Self :: dreg | Self :: dreg_low16 | Self :: dreg_low8 => types ! {
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"vfp2" : I64 , F64 , VecI8 ( 8 ) , VecI16 ( 4 ) , VecI32 ( 2 ) , VecI64 ( 1 ) , VecF32 ( 2 ) ;
@@ -88,20 +87,32 @@ fn frame_pointer_r7(
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}
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}
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+ fn not_thumb1 (
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+ _arch : InlineAsmArch ,
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+ mut has_feature : impl FnMut ( & str ) -> bool ,
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+ _target : & Target ,
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+ ) -> Result < ( ) , & ' static str > {
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+ if has_feature ( "thumb-mode" ) && !has_feature ( "thumb2" ) {
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+ Err ( "high registers (r8+) cannot be used in Thumb-1 code" )
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+ } else {
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+ Ok ( ( ) )
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+ }
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+ }
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+
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def_regs ! {
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Arm ArmInlineAsmReg ArmInlineAsmRegClass {
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- r0: reg, reg_thumb = [ "r0" , "a1" ] ,
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- r1: reg, reg_thumb = [ "r1" , "a2" ] ,
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- r2: reg, reg_thumb = [ "r2" , "a3" ] ,
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- r3: reg, reg_thumb = [ "r3" , "a4" ] ,
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- r4: reg, reg_thumb = [ "r4" , "v1" ] ,
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- r5: reg, reg_thumb = [ "r5" , "v2" ] ,
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- r7: reg, reg_thumb = [ "r7" , "v4" ] % frame_pointer_r7,
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- r8: reg = [ "r8" , "v5" ] ,
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- r10: reg = [ "r10" , "sl" ] ,
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+ r0: reg = [ "r0" , "a1" ] ,
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+ r1: reg = [ "r1" , "a2" ] ,
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+ r2: reg = [ "r2" , "a3" ] ,
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+ r3: reg = [ "r3" , "a4" ] ,
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+ r4: reg = [ "r4" , "v1" ] ,
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+ r5: reg = [ "r5" , "v2" ] ,
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+ r7: reg = [ "r7" , "v4" ] % frame_pointer_r7,
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+ r8: reg = [ "r8" , "v5" ] % not_thumb1 ,
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+ r10: reg = [ "r10" , "sl" ] % not_thumb1 ,
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r11: reg = [ "r11" , "fp" ] % frame_pointer_r11,
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- r12: reg = [ "r12" , "ip" ] ,
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- r14: reg = [ "r14" , "lr" ] ,
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+ r12: reg = [ "r12" , "ip" ] % not_thumb1 ,
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+ r14: reg = [ "r14" , "lr" ] % not_thumb1 ,
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s0: sreg, sreg_low16 = [ "s0" ] ,
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s1: sreg, sreg_low16 = [ "s1" ] ,
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s2: sreg, sreg_low16 = [ "s2" ] ,
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