adjust documented inline-asm register constraints

[Lokathor]

This change more clearly specifies how reg and reg_thumb work with ARM, Thumb2, and Thumb1 code.

Based upon the llvm documentation for register constraint codes.
To be clear, this just updates the docs to match what already happens with rustc/llvm.
No change in the compiler is required to make it match this new documentation.

[rust-highfive]

r? @steveklabnik

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[Lokathor]

(as discussed at the 2021-11-09 T-lang meeting)

cc @Amanieu and @joshtriplett

[Lokathor]

It's my understanding that Amaneau would prefer that the reg class not do separate things on thumb1 as compared to thumb2 and ARM, but LLVM already operates this way. If the full range of registers is allowed on thumb1 then it just leads to strange compile errors. Registers above r0-r7 aren't allowed in thumb1 with instructions other than add, mov, and cmp, so those registers shouldn't be allocated to thumb1 inline assembly by default.

If we want to allow the high registers to be used with thumb1 inline assembly, a separate register class could be made for that, but note that LLVM doesn't even actually support that use case at this time. There is not any register class you can provide to LLVM to make give you the high registers (r8 and above) with thumb1 code.

[Amanieu]

I'm actually starting to have second thoughts on the value of having a separate reg_thumb register class. I'm probably going to remove it before stabilization.

In any case, this PR accurately describes what currently happens.

@bors r+ rollup

[bors]

📌 Commit a306d35 has been approved by Amanieu