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A-MIRArea: Mid-level IR (MIR) - https://blog.rust-lang.org/2016/04/19/MIR.htmlArea: Mid-level IR (MIR) - https://blog.rust-lang.org/2016/04/19/MIR.htmlP-highHigh priorityHigh priorityT-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.
Description
fn good_loop() {
let mut should_break = false;
loop {
if *should_break {
break;
}
should_break = true;
}
}
has
bb1: {
StorageLive(_4); // scope 1 at test.rs:4:12: 4:24
_4 = _1; // scope 1 at test.rs:4:12: 4:24
StorageDead(_4); // scope 1 at test.rs:4:24: 4:24
if(_4) -> [true: bb2, false: bb3]; // scope 1 at test.rs:4:9: 6:10
}
as the generated MIR. The LLVM IR ends up being generated correctly, because _4
is determined to be an SSA-like lvalue, but I fear that there may also be cases where equivalent of _4
would be forced into an alloca (and generate incorrect IR, after some compiler change maybe?) and would certainly interfere with MIR optimisations and MIR borrowck.
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A-MIRArea: Mid-level IR (MIR) - https://blog.rust-lang.org/2016/04/19/MIR.htmlArea: Mid-level IR (MIR) - https://blog.rust-lang.org/2016/04/19/MIR.htmlP-highHigh priorityHigh priorityT-compilerRelevant to the compiler team, which will review and decide on the PR/issue.Relevant to the compiler team, which will review and decide on the PR/issue.